Alternatives and similar repositories for HB--tree-based-SA-scheme-for-analog-floorplan-design

Users that are interested in HB--tree-based-SA-scheme-for-analog-floorplan-design are comparing it to the libraries listed below

• mirkat1206 / Sequence-Pair-Floorplanner
  C++ implementation for Sequence Pair fixed-outline chip floorplanner
  ☆11Updated 2 years ago
• cuhk-eda / Xplace
  Xplace 3.0: An Extremely Fast, Extensible and Deterministic Placement Framework with Detailed-Routability and Timing Optimization
  ☆146Updated 5 months ago
• VidyaChhabria / ThermEDGe-and-IREDGe
  Encoder-decoder based generative networks for static and transient thermal analysis
  ☆22Updated 2 years ago
• ABKGroup / BlobPlacement
  ☆15Updated last year
• lamda-bbo / Open3DBench
  Official implementation of paper "Open3DBench: Open-Source Benchmark for 3D-IC Backend Implementation and PPA Evaluation".
  ☆66Updated 5 months ago
• bu-icsg / TAP-2.5D
  ☆37Updated 4 years ago
• PKU-IDEA / OpenPARF
  🕹 OpenPARF: An Open-Source Placement and Routing Framework for Large-Scale Heterogeneous FPGAs with Deep Learning Toolkit
  ☆161Updated 7 months ago
• EricLu1218 / Physical_Design_Automation
  NTHU CS6135 VLSI Physical Design Automation Course Projects (include Two-way Min-cut Partitioning, Fixed-outline Slicing Floorplan Design…
  ☆42Updated 2 months ago
• thu-nics / awesome_ai4eda
  ☆276Updated 4 years ago
• cuhk-eda / cu-gr
  CUGR, VLSI Global Routing Tool Developed by CUHK
  ☆139Updated 2 years ago
• lamda-bbo / Efficient-TDP
  Official implementation of DATE'25 paper "Timing-Driven Global Placement by Efficient Critical Path Extraction".
  ☆56Updated 5 months ago
• ycchen218 / EDA-Congestion-Prediction
  This is a deep-learning based model for Electronic Design Automation(EDA), predicting the congestion location.
  ☆21Updated last year
• cuhk-eda / CULS
  GPU-based logic synthesis tool
  ☆97Updated this week
• ABKGroup / PlacementEssentialReadings
  ☆58Updated 4 years ago
• cuhk-eda / cu-gr-2
  ☆47Updated last year
• cuhk-eda / dr-cu
  Dr. CU, VLSI Detailed Routing Tool Developed by CUHK
  ☆139Updated 2 years ago
• ai4eda / awesome-AI4EDA
  This repo awesome-AI4EDA contains the source for the webpage: https://ai4eda.github.io, which is a curated paper list of awesome AI for E…
  ☆172Updated 5 months ago
• geziangfinn / easyPlace
  Reimplementation of the VLSI placement algorithm: ePlace and ePlace-MS
  ☆53Updated last year
• Daikon-Sun / Physical-Design-for-Nanometer-ICs
  Assignments of Physical Design for Nanometer ICs (Spring 2017, Prof. Yao-Wen Chang)
  ☆43Updated 6 years ago
• TimingPredict / TimingPredict
  Official open source repository for "A Timing Engine Inspired Graph Neural Network Model for Pre-Routing Slack Prediction" (DAC 2022)
  ☆84Updated last year
• zslwyuan / AMF-Placer
  AMF-Placer 2.0: An open-source timing-driven analytical mixed-size FPGA placer of heterogeneous resources (LUT/FF/LUTRAM/MUX/CARRY/DSP/BR…
  ☆107Updated last year
• TILOS-AI-Institute / HypergraphPartitioning
  Hypergraph Partitioning: benchmarks, evaluators, best known solutions and codes
  ☆75Updated this week
• ABKGroup / TritonPart
  The first version of TritonPart
  ☆29Updated last year
• uvahotspot / HotSpot
  HotSpot v7.0 is an accurate and fast thermal model suitable for use in architectural studies.
  ☆141Updated 2 years ago
• recurme / Mixed-Cell-Height_legalizer
  ☆11Updated last year
• circuitnet / CircuitNet
  CircuitNet: An Open-Source Dataset for Machine Learning Applications in Electronic Design Automation (EDA)
  ☆421Updated 4 months ago
• pkuzjx / EDA-wiki
  EDA wiki
  ☆135Updated 3 weeks ago
• hkust-zhiyao / MasterRTL
  MasterRTL: A Pre-Synthesis PPA Estimation Framework for Any RTL Design
  ☆58Updated 6 months ago
• LQY404 / EDA-info
  the awesome work, project and lab of EDA (Electronic Design Automation). continue update...
  ☆25Updated last year
• cuhk-eda / GCS-Timer
  ☆24Updated 5 months ago