The-OpenROAD-Project / PDNSim
Power grid analysis
☆19Updated 4 years ago
Alternatives and similar repositories for PDNSim:
Users that are interested in PDNSim are comparing it to the libraries listed below
- Macro placement tool for OpenROAD flow☆23Updated 4 years ago
- UCSD Sizer for leakage/dynamic power recovery, timing recovery☆18Updated 6 years ago
- ☆29Updated 4 years ago
- ☆43Updated last year
- ☆22Updated 4 years ago
- Source codes and calibration scripts for clock tree synthesis☆40Updated 5 years ago
- LEF/DEF-based port of Iowa State's open-source FastRoute 4.1☆54Updated 4 years ago
- This GitHub repo is for the OpenROAD and CircuitOps Tutorial at ASP-DAC 2024☆44Updated 3 months ago
- An analytical VLSI placer☆28Updated 3 years ago
- Logic synthesis and ABC based optimization☆49Updated last week
- Global Router Built for ICCAD Contest 2019☆31Updated 5 years ago
- Open Source Detailed Placement engine☆11Updated 5 years ago
- Delay Calculation ToolKit☆31Updated 2 years ago
- A parallel global router using the Galois framework☆27Updated last year
- EDA physical synthesis optimization kit☆52Updated last year
- UCSD Detailed Router☆85Updated 4 years ago
- A Fast C++ Header-only Parser for Standard Parasitic Exchange Format (SPEF).☆55Updated 2 years ago
- DATC RDF☆49Updated 4 years ago
- Open Source Detailed Placement engine☆38Updated 5 years ago
- Public repository for Task 6 of OpenROAD project. ML-based PDN synthesis and optimization.☆33Updated last year
- ☆25Updated 2 years ago
- VLSI EDA Global Router☆72Updated 7 years ago
- Collection of digital hardware modules & projects (benchmarks)☆54Updated 5 months ago
- SMT-based-STDCELL-Layout-Generator☆17Updated 3 years ago
- SMT-based Simultaneous Place-&-Route for Standard Cell Synthesis for PROBE 2.0☆17Updated 4 years ago
- ☆30Updated 3 years ago
- Annealing-based PCB placement tool☆37Updated 4 years ago
- ☆15Updated 4 years ago
- ☆34Updated 5 years ago
- Open source process design kit for 28nm open process☆54Updated last year