RTimothyEdwards / qrouter
Qrouter detail router for digital ASIC designs
☆56Updated 5 months ago
Alternatives and similar repositories for qrouter:
Users that are interested in qrouter are comparing it to the libraries listed below
- Netgen complete LVS tool for comparing SPICE or verilog netlists☆113Updated this week
- BAG framework☆40Updated 7 months ago
- Builds, flow and designs for the alpha release☆54Updated 5 years ago
- ☆60Updated 2 weeks ago
- KLayout technology files for Skywater SKY130☆39Updated last year
- XSCHEM symbol libraries for the Google-Skywater 130nm process design kit.☆60Updated last week
- ☆110Updated 4 years ago
- ☆31Updated last year
- Coriolis VLSI EDA Tool (LIP6)☆62Updated 3 weeks ago
- Tatum: A Fast, Flexible Static Timing Analysis (STA) Engine for Digital Circuits☆56Updated 9 months ago
- IO and Pin Placer for Floorplan-Placement Subflow☆22Updated 4 years ago
- SystemVerilog frontend for Yosys☆79Updated last week
- Source codes and calibration scripts for clock tree synthesis☆40Updated 5 years ago
- AMC: Asynchronous Memory Compiler☆48Updated 4 years ago
- A Standalone Structural Verilog Parser☆89Updated 2 years ago
- ☆79Updated 2 years ago
- UCSD Detailed Router☆84Updated 4 years ago
- ☆53Updated last year
- ☆41Updated 5 years ago
- ☆46Updated last month
- LEF/DEF-based port of Iowa State's open-source FastRoute 4.1☆53Updated 4 years ago
- Open Source tool to build liberty files and for Characterizing Standard Cells.☆25Updated 4 years ago
- ☆39Updated 11 months ago
- Intel's Analog Detailed Router☆38Updated 5 years ago
- IDEA project source files☆103Updated 4 months ago
- A collection of big designs to run post-synthesis simulations with yosys☆49Updated 9 years ago
- UCSD Sizer for leakage/dynamic power recovery, timing recovery☆18Updated 6 years ago
- ☆22Updated 4 years ago
- Circuit Automatic Characterization Engine☆47Updated last month
- ☆103Updated 5 years ago