LQY404 / EDA-info
the awesome work, project and lab of EDA (Electronic Design Automation). continue update...
☆19Updated 2 months ago
Related projects ⓘ
Alternatives and complementary repositories for EDA-info
- SAGERoute: Synergistic Analog Routing Considering Geometric and Electrical Constraints with Manual Design Compatibility (DATE2023)☆19Updated last year
- BoxRouter2.0 is a new global router for ultimate routability. It is inspired by BoxRouter [1], but can perform multi-layer routing with 2…☆20Updated 5 years ago
- Reimplementation of the VLSI placement algorithm: ePlace and ePlace-MS☆19Updated this week
- Dr. CU, VLSI Detailed Routing Tool Developed by CUHK☆128Updated last year
- ☆35Updated 10 months ago
- CUGR, VLSI Global Routing Tool Developed by CUHK☆121Updated last year
- ☆17Updated last year
- Analog Placement Quality Prediction☆19Updated last year
- REST, a reinforcement learning framework for constructing rectilinear Steiner Minimum tree (RSMT)☆50Updated 2 years ago
- Artificial Netlist Generator☆32Updated 7 months ago
- ☆49Updated 3 years ago
- A parallel global router using the Galois framework☆25Updated last year
- This GitHub repo is for the OpenROAD and CircuitOps Tutorial at ASP-DAC 2024☆30Updated this week
- Xplace 2.0: An Extremely Fast, Extensible and Deterministic Placement Framework with Detailed-Routability Optimization☆97Updated 4 months ago
- ☆29Updated last year
- ☆25Updated 4 years ago
- VLSI EDA Global Router☆68Updated 6 years ago
- GPU-based logic synthesis tool☆67Updated 3 months ago
- Pin-Accessible Legalization for Mixed-Cell-Height Circuits☆26Updated 2 years ago
- ☆28Updated 2 years ago
- Global Router Built for ICCAD Contest 2019☆30Updated 4 years ago
- awesome-Analog-IC-Design-Automation☆29Updated last year
- This is a deep-learning based model for Electronic Design Automation(EDA), predicting the congestion location.☆19Updated 2 months ago
- ☆20Updated last month
- LEF/DEF-based port of Iowa State's open-source FastRoute 4.1☆52Updated 4 years ago
- A circuit-element level explainer to explain machine learning model's prediction on chip layouts.☆17Updated last year
- UCSD Detailed Router☆79Updated 3 years ago
- ☆23Updated 3 years ago
- Rsyn – An Extensible Physical Synthesis Framework☆122Updated 3 months ago
- Official open source repository for "A Timing Engine Inspired Graph Neural Network Model for Pre-Routing Slack Prediction" (DAC 2022)☆63Updated 2 months ago