SAGERoute: Synergistic Analog Routing Considering Geometric and Electrical Constraints with Manual Design Compatibility (DATE2023)
☆28Apr 8, 2023Updated 2 years ago
Alternatives and similar repositories for SAGERoute
Users that are interested in SAGERoute are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Intel's Analog Detailed Router☆40Jul 18, 2019Updated 6 years ago
- the awesome work, project and lab of EDA (Electronic Design Automation). continue update...☆26Aug 29, 2024Updated last year
- Machine Generated Analog IC Layout☆277Apr 24, 2024Updated last year
- Analog IC symmetry extraction benchmark of AncstrGNN☆10Aug 19, 2024Updated last year
- Flute3 is an open-source rectilinear Steiner minimum tree heuristic from Iowa State, with UFRGS improvements☆28Dec 16, 2020Updated 5 years ago
- Library for VLSI CAD Design Useful parsers and solvers' api are implemented.☆194May 19, 2025Updated 10 months ago
- Layout Symmetry Annotation for Analog Circuits with GraphNeural Networks☆16Apr 7, 2023Updated 2 years ago
- ☆18May 23, 2021Updated 4 years ago
- A project to perform the VLSI Physical Design Flow steps of partitioning, floorplan, placement and routing.☆13Jun 9, 2021Updated 4 years ago
- Benchmark Generator for Global Routing☆13Jul 18, 2019Updated 6 years ago
- Official implementation of MacroRank: Ranking Macro Placement Solutions Leveraging Translation Equivariancy (ASP-DAC 2023)☆17Jun 3, 2023Updated 2 years ago
- REST, a reinforcement learning framework for constructing rectilinear Steiner Minimum tree (RSMT)☆60Apr 22, 2022Updated 3 years ago
- ☆11Feb 1, 2022Updated 4 years ago
- Global Router Built for ICCAD Contest 2019☆34Mar 20, 2020Updated 6 years ago
- Qrouter detail router for digital ASIC designs☆57Nov 13, 2025Updated 4 months ago
- ☆21Nov 29, 2022Updated 3 years ago
- RePlAce global placement tool☆247Aug 13, 2020Updated 5 years ago
- LLM-Enhanced Bayesian Optimization for Efficient Analog Constraint Generation☆31Oct 28, 2024Updated last year
- CUGR, VLSI Global Routing Tool Developed by CUHK☆145Feb 27, 2023Updated 3 years ago
- 🕹 OpenPARF: An Open-Source Placement and Routing Framework for Large-Scale Heterogeneous FPGAs with Deep Learning Toolkit☆172Apr 25, 2025Updated 11 months ago
- Logic optimization and technology mapping tool.☆20Oct 12, 2023Updated 2 years ago
- ☆342Jan 13, 2026Updated 2 months ago
- Reimplementation of the VLSI placement algorithm: ePlace and ePlace-MS☆53Nov 4, 2024Updated last year
- ILP SAT Detailed Router☆13Apr 14, 2020Updated 5 years ago
- ☆33Aug 23, 2022Updated 3 years ago
- Applying Deep Q-learning for Global Routing☆130Sep 15, 2020Updated 5 years ago
- [ICCAD 22]DeePEB: A neural network based PEB solver☆12Feb 17, 2023Updated 3 years ago
- Courseworks of CS6165 VLSI Physical Design Automation, NTHU.☆49Jan 23, 2021Updated 5 years ago
- ☆24Dec 1, 2025Updated 3 months ago
- LLM Evaluation Framework for Hardware Design Using Python-Embedded DSLs☆17Aug 26, 2024Updated last year
- An analytical VLSI placer☆31Nov 22, 2021Updated 4 years ago
- Official code repo for the paper "MemGUI-Bench: Benchmarking Memory of Mobile GUI Agents in Dynamic Environments"☆33Mar 9, 2026Updated 2 weeks ago
- A Design Rule Checker with GPU Acceleration☆61Sep 15, 2023Updated 2 years ago
- CircuitNet: An Open-Source Dataset for Machine Learning Applications in Electronic Design Automation (EDA)☆458Jul 17, 2025Updated 8 months ago
- Comparative Analysis of Graph Neural Networks for Node Regression task on Wiki-Squirrel dataset (Bachelor's Research Project)☆12Nov 6, 2025Updated 4 months ago
- BoxRouter2.0 is a new global router for ultimate routability. It is inspired by BoxRouter [1], but can perform multi-layer routing with 2…☆21Dec 20, 2018Updated 7 years ago
- This place provide different SRAM cells netlist to be simulated with HSpice tool in sub-20nm FinFET technologies.☆12Dec 31, 2020Updated 5 years ago
- ☆21May 25, 2023Updated 2 years ago
- Export yolov5 model to run on cpu using tflite☆14Aug 12, 2021Updated 4 years ago