Alternatives and similar repositories for SAGERoute:

Users that are interested in SAGERoute are comparing it to the libraries listed below

• LQY404 / EDA-info
  the awesome work, project and lab of EDA (Electronic Design Automation). continue update...
  ☆22Updated 6 months ago
• magical-eda / UT-AnLay
  Analog Placement Quality Prediction
  ☆20Updated last year
• ABKGroup / PROBE_SMT_AutoCell
  ☆17Updated last year
• ieee-ceda-datc / datc-rdf-Metrics4ML
  ☆28Updated 3 years ago
• ABKGroup / PlacementEssentialReadings
  ☆52Updated 4 years ago
• cuhk-eda / cu-gr
  CUGR, VLSI Global Routing Tool Developed by CUHK
  ☆128Updated 2 years ago
• ieee-ceda-datc / RDF-2019
  DATC RDF
  ☆49Updated 4 years ago
• UTDA-group / BoxRouter
  BoxRouter2.0 is a new global router for ultimate routability. It is inspired by BoxRouter [1], but can perform multi-layer routing with 2…
  ☆20Updated 6 years ago
• cuhk-eda / CULS
  GPU-based logic synthesis tool
  ☆81Updated 7 months ago
• cuhk-eda / Xplace
  Xplace 2.0: An Extremely Fast, Extensible and Deterministic Placement Framework with Detailed-Routability Optimization
  ☆116Updated 2 months ago
• ASU-VDA-Lab / 2024_ICCAD_Contest_Gate_Sizing_Benchmark
  ☆19Updated 4 months ago
• zslwyuan / AutoCellLibX
  AutoCellLibX: Automated Standard Cell Library Extension Based on Pattern Mining
  ☆12Updated 2 years ago
• geziangfinn / easyPlace
  Reimplementation of the VLSI placement algorithm: ePlace and ePlace-MS
  ☆28Updated 4 months ago
• jinwookjungs / datc_robust_design_flow
  DATC Robust Design Flow.
  ☆37Updated 5 years ago
• opendrc / opendrc
  A Design Rule Checker with GPU Acceleration
  ☆47Updated last year
• AUCOHL / OGRE
  Global Router Built for ICCAD Contest 2019
  ☆30Updated 4 years ago
• TILOS-AI-Institute / MLCAD-2023-FPGA-Macro-Placement-Contest
  ☆29Updated last year
• ALIGN-analoglayout / AnalogDetailedRouter
  Intel's Analog Detailed Router
  ☆38Updated 5 years ago
• daeyeon22 / artificial_netlist_generator
  Artificial Netlist Generator
  ☆36Updated 11 months ago
• ABKGroup / PROBE3.0
  ☆39Updated 11 months ago
• cuhk-eda / ripple
  Pin-Accessible Legalization for Mixed-Cell-Height Circuits
  ☆26Updated 3 years ago
• santoshsmalagi / Benchmarks
  A collection of ISCAS,ITC,TAU and other Benchmark Circuits for EDA tool evaluation.
  ☆43Updated 2 months ago
• rachelselinar / DREAMPlaceFPGA
  An Open-Source Analytical Placer for Large Scale Heterogeneous FPGAs using Deep-Learning Toolkit
  ☆79Updated 2 months ago
• sathvikbhat / vlsi_physical_design_automation
  A project to perform the VLSI Physical Design Flow steps of partitioning, floorplan, placement and routing.
  ☆11Updated 3 years ago
• baloneymath / AncstrGNN
  ☆15Updated 3 years ago
• RsynTeam / rsyn-x
  Rsyn – An Extensible Physical Synthesis Framework
  ☆123Updated 7 months ago
• jinwookjungs / lefdef_util
  A LEF/DEF Utility.
  ☆27Updated 5 years ago
• ai4eda / awesome-AI4EDA
  This repo awesome-AI4EDA contains the source for the webpage: https://ai4eda.github.io, which is a curated paper list of awesome AI for E…
  ☆142Updated 8 months ago
• cuhk-eda / dr-cu
  Dr. CU, VLSI Detailed Routing Tool Developed by CUHK
  ☆132Updated last year
• UMN-EDA / BeGAN-benchmarks
  ☆24Updated last year