PKU-IDEA / SAGERouteLinks
SAGERoute: Synergistic Analog Routing Considering Geometric and Electrical Constraints with Manual Design Compatibility (DATE2023)
☆21Updated 2 years ago
Alternatives and similar repositories for SAGERoute
Users that are interested in SAGERoute are comparing it to the libraries listed below
Sorting:
- UCSD Detailed Router☆90Updated 4 years ago
- CUGR, VLSI Global Routing Tool Developed by CUHK☆137Updated 2 years ago
- the awesome work, project and lab of EDA (Electronic Design Automation). continue update...☆24Updated last year
- Global Router Built for ICCAD Contest 2019☆33Updated 5 years ago
- LEF/DEF-based port of Iowa State's open-source FastRoute 4.1☆58Updated 5 years ago
- DATC RDF☆50Updated 5 years ago
- VLSI EDA Global Router☆75Updated 7 years ago
- Dr. CU, VLSI Detailed Routing Tool Developed by CUHK☆137Updated 2 years ago
- 🕹 OpenPARF: An Open-Source Placement and Routing Framework for Large-Scale Heterogeneous FPGAs with Deep Learning Toolkit☆154Updated 4 months ago
- Xplace 3.0: An Extremely Fast, Extensible and Deterministic Placement Framework with Detailed-Routability and Timing Optimization☆136Updated 2 months ago
- FAN (fan-out-oriented) ATPG (Automatic Test Pattern Generation) and Fault Simulation command line tool☆93Updated last month
- ☆20Updated 2 years ago
- BoxRouter2.0 is a new global router for ultimate routability. It is inspired by BoxRouter [1], but can perform multi-layer routing with 2…☆21Updated 6 years ago
- Library for VLSI CAD Design Useful parsers and solvers' api are implemented.☆175Updated 3 months ago
- An Open-Source Analytical Placer for Large Scale Heterogeneous FPGAs using Deep-Learning Toolkit☆84Updated 4 months ago
- Machine Generated Analog IC Layout☆248Updated last year
- ☆31Updated 3 years ago
- Material for OpenROAD Tutorial at DAC 2020☆47Updated 2 years ago
- Analog Placement Quality Prediction☆24Updated 2 years ago
- A parallel global router using the Galois framework☆29Updated 2 years ago
- ☆23Updated 9 months ago
- Official implementation of DATE'25 paper "Timing-Driven Global Placement by Efficient Critical Path Extraction".☆50Updated 2 months ago
- AMF-Placer 2.0: An open-source timing-driven analytical mixed-size FPGA placer of heterogeneous resources (LUT/FF/LUTRAM/MUX/CARRY/DSP/BR…☆105Updated last year
- ☆34Updated 4 years ago
- Rsyn – An Extensible Physical Synthesis Framework☆129Updated last year
- A Design Rule Checker with GPU Acceleration☆53Updated last year
- Incremental Timing-Driven Placement, problem C of ICCAD contest 2015☆15Updated 7 years ago
- Reimplementation of the VLSI placement algorithm: ePlace and ePlace-MS☆48Updated 9 months ago
- Courseworks of CS6165 VLSI Physical Design Automation, NTHU.☆47Updated 4 years ago
- GPU-based logic synthesis tool☆90Updated 3 weeks ago