PKU-IDEA / SAGERouteLinks
SAGERoute: Synergistic Analog Routing Considering Geometric and Electrical Constraints with Manual Design Compatibility (DATE2023)
☆22Updated 2 years ago
Alternatives and similar repositories for SAGERoute
Users that are interested in SAGERoute are comparing it to the libraries listed below
Sorting:
- Xplace 3.0: An Extremely Fast, Extensible and Deterministic Placement Framework with Detailed-Routability and Timing Optimization☆141Updated 4 months ago
- CUGR, VLSI Global Routing Tool Developed by CUHK☆138Updated 2 years ago
- Library for VLSI CAD Design Useful parsers and solvers' api are implemented.☆183Updated 5 months ago
- the awesome work, project and lab of EDA (Electronic Design Automation). continue update...☆24Updated last year
- UCSD Detailed Router☆91Updated 4 years ago
- An Open-Source Analytical Placer for Large Scale Heterogeneous FPGAs using Deep-Learning Toolkit☆85Updated 6 months ago
- Dr. CU, VLSI Detailed Routing Tool Developed by CUHK☆137Updated 2 years ago
- Analog Placement Quality Prediction☆25Updated 2 years ago
- ☆31Updated 3 years ago
- 🕹 OpenPARF: An Open-Source Placement and Routing Framework for Large-Scale Heterogeneous FPGAs with Deep Learning Toolkit☆159Updated 6 months ago
- VLSI EDA Global Router☆75Updated 7 years ago
- Global Router Built for ICCAD Contest 2019☆32Updated 5 years ago
- BoxRouter2.0 is a new global router for ultimate routability. It is inspired by BoxRouter [1], but can perform multi-layer routing with 2…☆21Updated 6 years ago
- LEF/DEF-based port of Iowa State's open-source FastRoute 4.1☆58Updated 5 years ago
- DATC RDF☆50Updated 5 years ago
- ☆47Updated last year
- ☆90Updated 2 months ago
- This GitHub repo is for the OpenROAD and CircuitOps Tutorial at ASP-DAC 2024☆52Updated 9 months ago
- ☆31Updated 2 years ago
- ☆61Updated this week
- ☆23Updated 11 months ago
- Circuit release of the MAGICAL project☆39Updated 5 years ago
- ☆20Updated 2 years ago
- ☆77Updated 4 months ago
- ☆88Updated 4 months ago
- This is a deep-learning based model for Electronic Design Automation(EDA), predicting the IR drop location on the chip.☆31Updated 2 years ago
- Material for OpenROAD Tutorial at DAC 2020☆46Updated 2 years ago
- Official implementation of DATE'25 paper "Timing-Driven Global Placement by Efficient Critical Path Extraction".☆54Updated 4 months ago
- Machine Generated Analog IC Layout☆256Updated last year
- Reimplementation of the VLSI placement algorithm: ePlace and ePlace-MS☆53Updated 11 months ago