stanford-centaur / ponoLinks
Pono: A flexible and extensible SMT-based model checker
☆110Updated this week
Alternatives and similar repositories for pono
Users that are interested in pono are comparing it to the libraries listed below
Sorting:
- Reads a state transition system and performs property checking☆87Updated 3 weeks ago
- The HW-CBMC and EBMC Model Checkers for Verilog☆83Updated this week
- IC3 reference implementation: a short, simple, fairly competitive implementation of IC3. Read it, tune it, extend it, play with it.☆60Updated 10 years ago
- CoreIR Symbolic Analyzer☆74Updated 4 years ago
- Hardware Formal Verification Tool☆67Updated 3 weeks ago
- The source code to the Voss II Hardware Verification Suite☆56Updated 2 weeks ago
- rIC3 model checker for Hardware Model Checking Competition 2024(HWMCC'24) submission☆12Updated 2 months ago
- A generic parser and tool package for the BTOR2 format.☆42Updated 2 weeks ago
- A generic C++ API for SMT solving. It provides abstract classes which can be implemented by different SMT solvers.☆129Updated this week
- SMTSampler: Efficient Stimulus Generation from Complex SMT Constraints☆29Updated 6 years ago
- BTOR2 MLIR project☆26Updated last year
- Recent papers related to hardware formal verification.☆73Updated 2 years ago
- A Modeling and Verification Platform for SoCs using ILAs☆77Updated last year
- AMulet 2. - A better AIG Multiplier Examination Tool☆26Updated 2 years ago
- Collection for submission (Hardware Model Checking Benchmark)☆10Updated 11 months ago
- PyCaliper is Python-based tooling infrastructure that allows the verification and synthesis of specifications (properties) for RTL (e.g.,…☆22Updated 3 months ago
- Random Generator of Btor2 Files☆10Updated 2 years ago
- AIGER And-Inverter-Graph Library☆88Updated 2 months ago
- Verilog development and verification project for HOL4☆27Updated 5 months ago
- A Platform for High-Level Parametric Hardware Specification and its Modular Verification☆161Updated 2 months ago
- A fork of the Kissat SAT solver with additional features. Supports incremental solving.☆15Updated 3 years ago
- ☆35Updated 2 months ago
- A formally verified high-level synthesis tool based on CompCert and written in Coq.☆93Updated 3 weeks ago
- UCLID5: formal modeling, verification, and synthesis of computational systems☆149Updated 2 months ago
- CUDD Decision Diagram Package☆143Updated last month
- FPGA synthesis tool powered by program synthesis☆52Updated 2 months ago
- Bitwuzla is a Satisfiability Modulo Theories (SMT) solver for the theories of fixed-size bit-vectors, floating-point arithmetic, arrays a…☆281Updated this week
- A tool for checking the contract satisfaction for hardware designs☆11Updated 2 weeks ago
- A tutorial for setting up Symbolic Quick Error Detection (SQED) using the model checker, CoSA, on the Ride Core☆12Updated 6 years ago
- Approximate Model Counter☆80Updated 2 weeks ago