SystemVerilog file list pruner
☆19Oct 19, 2026Updated last week
Alternatives and similar repositories for prunefl
Users that are interested in prunefl are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- ROHD Wave Viewer is a waveform viewer Flutter app, part of the ROHD ecosystem. It works in-browser, integrated as a Flutter widget, used …☆14Updated this week
- APB UVC ported to Verilator☆11Nov 19, 2023Updated 2 years ago
- Circuit Automatic Characterization Engine☆16Sep 24, 2026Updated last month
- FPGA systolic array AI engine☆38Jan 2, 2026Updated 9 months ago
- Coverview☆36Oct 5, 2026Updated 3 weeks ago
- AI Agents on DigitalOcean Gradient AI Platform • AdBuild production-ready AI agents using customizable tools or access multiple LLMs through a single endpoint. Create custom knowledge bases or connect external data.
- This repository provides an automated shell script to set up a Verilator + UVM-based workflow using the [RTL2UVM](https://github.com/rpja…☆21Oct 21, 2025Updated last year
- ☆18Jun 22, 2026Updated 4 months ago
- ☆15May 24, 2025Updated last year
- Linter for SystemVerilog Assertions (SVA). Following the philosophy of BYOL - Build Your Own Linter, SVALint is an example of ho users ca…☆22Aug 23, 2026Updated 2 months ago
- A novel Design-for-Test flow using LibreLane☆50May 9, 2026Updated 5 months ago
- Summer School Week 1 & 2 repo☆12Jul 1, 2022Updated 4 years ago
- A Verilog implementation of Multi-bit-throughput LFSR with an detailed document about LFSRs for HW design engineers☆10Jan 2, 2026Updated 9 months ago
- wafer.space GF180MCU Run 1☆42Updated this week
- Yosys plugin for logic locking and supply-chain security☆25Apr 5, 2025Updated last year
- Virtual machines for every use case on DigitalOcean • AdGet dependable uptime with 99.99% SLA, simple security tools, and predictable monthly pricing with DigitalOcean's virtual machines, called Droplets.
- PyCacheGen: A Highly Configurable Open-Source Generator for Synthesizable Caches☆18Dec 14, 2025Updated 10 months ago
- ☆13Aug 24, 2026Updated 2 months ago
- ☆13Aug 17, 2026Updated 2 months ago
- A PCIe RTL implementation☆26Aug 16, 2026Updated 2 months ago
- ☆42Oct 16, 2026Updated 2 weeks ago
- Tranining Completion Project : : Verification of AXI Direct Memory Access (DMA) using UVM☆52Jul 11, 2025Updated last year
- VS Code extension for SystemVerilog design navigation, RTL tracing, schematic viewer, and waveform integration☆66Jul 25, 2026Updated 3 months ago
- Waveform Viewer Extension for VScode☆363Updated this week
- RTLMeter benchmark suite☆34Updated this week
- End-to-end encrypted cloud storage - Proton Drive • AdSpecial offer: 40% Off Yearly / 80% Off First Month. Protect your most important files, photos, and documents from prying eyes.
- Equivalence checking with Yosys☆66Oct 20, 2026Updated last week
- ☆48Oct 6, 2026Updated 3 weeks ago
- Systemverilog and UVM exercises inspired by ziglings☆36Updated this week
- OpenSoC Fabric - A Network-On-Chip Generator☆18Jun 12, 2017Updated 9 years ago
- Generates a SystemVerilog assertion interface for a given SV RTL design☆20Mar 23, 2025Updated last year
- ☆25Jun 23, 2024Updated 2 years ago
- Dyno-IR Monorepo. High-Performance Compiler Framework for HW Synthesis & Beyond.☆17Updated this week
- An open-source, JEDEC JESD270-4A-compliant HBM4 memory subsystem (controller + PHY-shim + DFT + RAS + security wrapper) tightly coupled t…☆27Jun 14, 2026Updated 4 months ago
- Debug waveforms with GDB☆33Nov 12, 2025Updated 11 months ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- openENOC is an open-source Ethernet-based NoC for scalable MPSoC systems, using Layer-2 frame switching to connect CPUs, accelerators and…☆28Oct 23, 2026Updated last week
- Open-Hardware implementation of the icsprout55-pdk☆18Oct 10, 2026Updated 2 weeks ago
- A Formal Verification Methodology to lower the adoption barriers for Formal Verification of ASIC and FPGA designs in the Space sector (th…☆25Jun 29, 2026Updated 4 months ago
- OpenLayout: an open-source custom IC design environment (KLayout, xschem, ngspice, FasterCap). ASAP7 today, support for more PDKs coming.☆19Updated this week
- A collection of cryptographic algorthms implemented in SystemVerilog☆20Jun 7, 2018Updated 8 years ago
- An Open-Source Full-Custom Silicon Compiler for High-Performance FPGA Fabrics☆21Aug 25, 2026Updated 2 months ago
- TuRTLe: A Unified Evaluation of LLMs for RTL Generation 🐢 (MLCAD 2025, ACM TODAES 2026)☆53Jul 22, 2026Updated 3 months ago