SystemVerilog file list pruner
☆18Aug 2, 2026Updated last week
Alternatives and similar repositories for prunefl
Users that are interested in prunefl are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- FPGA systolic array AI engine☆36Jan 2, 2026Updated 7 months ago
- Coverview☆32Updated this week
- This repository provides an automated shell script to set up a Verilator + UVM-based workflow using the [RTL2UVM](https://github.com/rpja…☆21Oct 21, 2025Updated 9 months ago
- ☆17Jun 22, 2026Updated last month
- ☆15May 24, 2025Updated last year
- Managed Kubernetes at scale on DigitalOcean • AdDigitalOcean Kubernetes includes the control plane, bandwidth allowance, container registry, automatic updates, and more for free.
- A novel Design-for-Test flow using LibreLane☆45May 9, 2026Updated 3 months ago
- Linter for SystemVerilog Assertions (SVA). Following the philosophy of BYOL - Build Your Own Linter, SVALint is an example of ho users ca…☆21Sep 10, 2025Updated 11 months ago
- wafer.space GF180MCU Run 1☆38Apr 27, 2026Updated 3 months ago
- VS Code extension for SystemVerilog design navigation, RTL tracing, schematic viewer, and waveform integration☆58Jul 25, 2026Updated 2 weeks ago
- Yosys plugin for logic locking and supply-chain security☆24Apr 5, 2025Updated last year
- PyCacheGen: A Highly Configurable Open-Source Generator for Synthesizable Caches☆18Dec 14, 2025Updated 7 months ago
- Summer School Week 1 & 2 repo☆12Jul 1, 2022Updated 4 years ago
- An open-source, JEDEC JESD270-4A-compliant HBM4 memory subsystem (controller + PHY-shim + DFT + RAS + security wrapper) tightly coupled t…☆22Jun 14, 2026Updated last month
- ☆37Jul 23, 2026Updated 2 weeks ago
- AI Agents on DigitalOcean Gradient AI Platform • AdBuild production-ready AI agents using customizable tools or access multiple LLMs through a single endpoint. Create custom knowledge bases or connect external data.
- Tranining Completion Project : : Verification of AXI Direct Memory Access (DMA) using UVM☆50Jul 11, 2025Updated last year
- RTLMeter benchmark suite☆31Jul 21, 2026Updated 3 weeks ago
- Waveform Viewer Extension for VScode☆352Aug 3, 2026Updated last week
- TuRTLe: A Unified Evaluation of LLMs for RTL Generation 🐢 (MLCAD 2025, ACM TODAES 2026)☆48Jul 22, 2026Updated 2 weeks ago
- Generates a SystemVerilog assertion interface for a given SV RTL design☆20Mar 23, 2025Updated last year
- Build infrastructure for class-wide tapeout for 18-224/624 Intro to Open Source Chip Design, Spring 2023☆21Aug 10, 2023Updated 3 years ago
- An Open-Source Full-Custom Silicon Compiler for High-Performance FPGA Fabrics☆18Jul 31, 2026Updated last week
- ☆47Jul 31, 2026Updated last week
- OpenSoC Fabric - A Network-On-Chip Generator☆17Jun 12, 2017Updated 9 years ago
- Proton VPN Special Offer - Get 70% off • AdSpecial partner offer. Trusted by over 100 million users worldwide. Tested, Approved and Recommended by Experts.
- Debug waveforms with GDB☆33Nov 12, 2025Updated 8 months ago
- A Formal Verification Methodology to lower the adoption barriers for Formal Verification of ASIC and FPGA designs in the Space sector (th…☆25Jun 29, 2026Updated last month
- Open-source PDK version manager☆57Jul 9, 2026Updated last month
- Curriculum for a university course to teach chip design using open source EDA tools☆160Oct 21, 2023Updated 2 years ago
- A collection of cryptographic algorthms implemented in SystemVerilog☆20Jun 7, 2018Updated 8 years ago
- Z-Core - A Lightweight RISC-V Processor (RV32IMZicsr)☆15Jun 26, 2026Updated last month
- A repository aggregating links to essential documentation, tutorials, and research papers for hardware Design Verification.☆66Jun 7, 2026Updated 2 months ago
- Catalyst N1 — Open source neuromorphic processor (Loihi 1 parity). 128 cores, 131K neurons, 14-opcode learning ISA, FPGA-validated on AWS…☆43Jun 2, 2026Updated 2 months ago
- Greyhound on IHP SG13G2 0.13 μm BiCMOS process☆107Jul 1, 2026Updated last month
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- Open source ISS and logic RISC-V 32 bit project☆63Jan 20, 2026Updated 6 months ago
- FPGA synthesis tool powered by program synthesis☆56Dec 15, 2025Updated 7 months ago
- Making cocotb testbenches that bit easier☆41Feb 28, 2026Updated 5 months ago
- Digital Design Equivalence Checking☆92Updated this week
- A verilog hardware description model of LLM for FPGA / SoC - runs newest LLM models☆27Jan 24, 2026Updated 6 months ago
- Fabric generator and CAD tools graphical frontend☆18Aug 5, 2025Updated last year
- Integration test for entire CGRA flow☆12Jan 17, 2020Updated 6 years ago