ultraembedded / core_axi_cache
128KB AXI cache (32-bit in, 256-bit out)
☆48Updated 3 years ago
Alternatives and similar repositories for core_axi_cache:
Users that are interested in core_axi_cache are comparing it to the libraries listed below
- ☆50Updated 2 years ago
- ☆31Updated 5 years ago
- General Purpose AXI Direct Memory Access☆49Updated 11 months ago
- The memory model was leveraged from micron.☆22Updated 7 years ago
- verification of simple axi-based cache☆18Updated 5 years ago
- LCAI-TIHU HW is an AI inference processor which is comprised of RISC-V cpu, nvdla, NoC bus, PCIe module, DDR, SRAM, bootROM, DMA and peri …☆36Updated 2 years ago
- SoC Based on ARM Cortex-M3☆30Updated 2 weeks ago
- Xilinx AXI VIP example of use☆37Updated 4 years ago
- Prototype-network-on-chip (ProNoC) is an EDA tool that facilitates prototyping of custom heterogeneous NoC-based many-core-SoC (MCSoC).☆54Updated last month
- ☆19Updated 2 years ago
- AXI Interconnect☆47Updated 3 years ago
- DDR5 PHY Graduation project (Verification Team) under supervision of Si-Vision☆53Updated last year
- ☆27Updated 4 years ago
- System Verilog and Emulation. Written all the five channels.☆33Updated 8 years ago
- A generic implementation of AMBA AXI4 communication protocol. The design provides a master, a slave and an interconnect with multiple mas…☆38Updated 2 years ago
- Implementation of the PCIe physical layer☆37Updated 3 months ago
- A verilog implementation for Network-on-Chip☆73Updated 7 years ago
- AXI master to AHB slave, support INCR/WRAP, out of standing, do not advanced feature such as support out of order, retry, split, etc☆39Updated 3 years ago
- DMA Hardware Description with Verilog☆14Updated 5 years ago
- This repository has a list of collaterals needed for ICC2 workshop. It has a modified version of raven_soc which was taped-out by Efables…☆31Updated 4 years ago
- DDR3 SDRAM Memory Controller Design & Synthesis using System Verilog☆31Updated 6 years ago
- AXI4 BFM in Verilog☆32Updated 8 years ago
- ☆55Updated 4 years ago
- IEEE 754 single and double precision floating point library in systemverilog and vhdl☆65Updated 4 months ago
- Parameterised Asynchronous AHB3-Lite to APB4 Bridge.☆42Updated 11 months ago
- ☆21Updated 5 years ago
- UART -> AXI Bridge☆60Updated 3 years ago
- HLS for Networks-on-Chip☆34Updated 4 years ago
- SystemVerilog modules and classes commonly used for verification☆47Updated 3 months ago
- ☆26Updated 5 years ago