ultraembedded / core_axi_cache
128KB AXI cache (32-bit in, 256-bit out)
☆48Updated 3 years ago
Alternatives and similar repositories for core_axi_cache:
Users that are interested in core_axi_cache are comparing it to the libraries listed below
- Prototype-network-on-chip (ProNoC) is an EDA tool that facilitates prototyping of custom heterogeneous NoC-based many-core-SoC (MCSoC).☆50Updated 2 weeks ago
- ☆29Updated 5 years ago
- General Purpose AXI Direct Memory Access☆48Updated 9 months ago
- verification of simple axi-based cache☆18Updated 5 years ago
- ☆41Updated 2 years ago
- The memory model was leveraged from micron.☆22Updated 6 years ago
- ☆18Updated 2 years ago
- SoC Based on ARM Cortex-M3☆27Updated last month
- LCAI-TIHU HW is an AI inference processor which is comprised of RISC-V cpu, nvdla, NoC bus, PCIe module, DDR, SRAM, bootROM, DMA and peri…☆36Updated 2 years ago
- DDR3 SDRAM Memory Controller Design & Synthesis using System Verilog☆30Updated 6 years ago
- DDR5 PHY Graduation project (Verification Team) under supervision of Si-Vision☆44Updated 11 months ago
- ☆25Updated 4 years ago
- ☆53Updated 4 years ago
- System Verilog and Emulation. Written all the five channels.☆33Updated 7 years ago
- HDL code for a DDR4 memory controller implementing an Open Page Policy and Out of Order execution.☆73Updated 7 years ago
- A generic implementation of AMBA AXI4 communication protocol. The design provides a master, a slave and an interconnect with multiple mas…☆31Updated 2 years ago
- CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform☆19Updated last week
- AXI Interconnect☆47Updated 3 years ago
- RTL code of some arbitration algorithm☆13Updated 5 years ago
- Verilog Code and Logisim simulation of a Weighted Round Robit Arbiter circuit using digital components☆18Updated 6 years ago
- Implementation of the pipelined RISC V processor with many useful features as fully bypassing, dynamic branch prediction, single and mult…☆14Updated last year
- Generic FIFO implementation with optional FWFT☆55Updated 4 years ago
- This repository has a list of collaterals needed for ICC2 workshop. It has a modified version of raven_soc which was taped-out by Efables…☆30Updated 4 years ago
- A barebones 64-bit RISC-V micro-controller class CPU, implementing the I(nteger), M(ul/div), C(ompressed) and K(ryptography) extensions.☆44Updated 3 years ago
- SystemVerilog Direct Programming Interface (DPI) Tutorial☆49Updated 4 years ago
- The controller is a Verilog implementation through a state machine structure per Micro datasheet specifications, and connected to a prede…☆21Updated 6 years ago
- AXI master to AHB slave, support INCR/WRAP, out of standing, do not advanced feature such as support out of order, retry, split, etc☆36Updated 2 years ago
- A verilog implementation for Network-on-Chip☆73Updated 7 years ago
- AXI3 Bus Functional Models (Initiator & Target)☆28Updated 2 years ago
- Base on Synopsys platform using VCS,DC,ICC,PT.☆11Updated 3 years ago