MichaelBell / tinyQV
A Risc-V SoC for Tiny Tapeout
☆15Updated 2 weeks ago
Alternatives and similar repositories for tinyQV:
Users that are interested in tinyQV are comparing it to the libraries listed below
- RISC-V RV32E core designed for minimal area☆13Updated 4 months ago
- RISC-V SoC Physical Implementation in 180 nm CMOS with a Quark Core Based on FemtoRV32☆44Updated last year
- A simple risc-v CPU /GPU running on an Arty A7-100T FPGA board☆29Updated 3 years ago
- Convert an image to a GDS format for inclusion in a zerotoasic project☆13Updated 2 years ago
- A padring generator for ASICs☆25Updated last year
- A minimal-area RISC-V core with a scalable data path to 1, 2, 4, or 8 bits and manifold variants.☆89Updated 6 months ago
- tools to help make the most of the limited space we have on the Google sponsored Efabless shuttles☆35Updated 2 years ago
- Demo of how to use https://github.com/openXC7 tools (yosys+nextpnr-xilinx) to implement the HW side of a custom SoC with RISC-V CPU & our…☆24Updated last month
- ☆36Updated 2 years ago
- RISC-V Nox core☆62Updated 8 months ago
- FPGA based microcomputer sandbox for software and RTL experimentation☆53Updated this week
- Fabric generator and CAD tools graphical frontend☆12Updated last year
- A Python package for generating HDL wrappers and top modules for HDL sources☆32Updated last week
- KLayout technology files for ASAP7 FinFET educational process☆20Updated 2 years ago
- Wishbone interconnect utilities☆39Updated last month
- ☆33Updated 2 years ago
- USB virtual model in C++ for Verilog☆29Updated 5 months ago
- Quick'n'dirty FuseSoC+cocotb example☆18Updated 4 months ago
- ☆33Updated 4 years ago
- Dual-issue RV64IM processor for fun & learning☆59Updated last year
- Reusable Verilog 2005 components for FPGA designs☆40Updated last month
- Set up your GitHub Actions workflow with a OSS CAD Suite☆15Updated last year
- ☆31Updated 2 months ago
- FPGA250 aboard the eFabless Caravel☆29Updated 4 years ago
- ☆33Updated 4 months ago
- LunaPnR is a place and router for integrated circuits☆46Updated 4 months ago
- A pipelined RISC-V processor☆54Updated last year
- ☆66Updated 7 months ago
- Open source MPSoC running 620 MIPS (CHStone) of RISC-V (RV32iMC) programms on the ARTY board (XC7A35T).☆20Updated 5 years ago
- High speed C/C++ based behavioural VHDL/Verilog co-simulation memory model☆22Updated 4 months ago