MichaelBell / tinyQVLinks
A Risc-V SoC for Tiny Tapeout
☆43Updated last month
Alternatives and similar repositories for tinyQV
Users that are interested in tinyQV are comparing it to the libraries listed below
Sorting:
- RISC-V RV32E core designed for minimal area☆23Updated last year
- A minimal-area RISC-V core with a scalable data path to 1, 2, 4, or 8 bits and manifold variants.☆111Updated 3 weeks ago
- Reusable Verilog 2005 components for FPGA designs☆49Updated last month
- FPGA based microcomputer sandbox for software and RTL experimentation☆75Updated 2 weeks ago
- RISC-V processor with CPI=1 (every single instruction executed in a single clock cycle).☆22Updated this week
- Greyhound on IHP SG13G2 0.13 μm BiCMOS process☆77Updated 3 weeks ago
- ☆71Updated last year
- Demo of how to use https://github.com/openXC7 tools (yosys+nextpnr-xilinx) to implement the HW side of a custom SoC with RISC-V CPU & our…☆35Updated 10 months ago
- Wishbone interconnect utilities☆44Updated 3 weeks ago
- RISC-V SoC Physical Implementation in 180 nm CMOS with a Quark Core Based on FemtoRV32☆56Updated 2 years ago
- ☆15Updated 7 months ago
- Spicing up the first and (no longer) the only EU FPGA chip with a flashy new board, loaded with a suite of engaging demos and examples =>…☆85Updated 2 months ago
- A simple risc-v CPU /GPU running on an Arty A7-100T FPGA board☆32Updated 4 years ago
- 5-stage RISC-V CPU, originally developed for RISCBoy☆34Updated 2 years ago
- Generic FPGA SDRAM controller, originally made for AS4C4M16SA☆82Updated 5 years ago
- The ILA allows you to perform in-system debugging of your designs on the GateMate FPGA at runtime. All signals of your design inside the …☆58Updated 2 months ago
- RISC-V CPU implementation in Amaranth HDL (aka nMigen)☆33Updated last year
- A Fully Open-Source Verilog-to-PCB Flow☆26Updated last year
- RISC-V Processor written in Amaranth HDL☆39Updated 3 years ago
- LunaPnR is a place and router for integrated circuits☆47Updated 5 months ago
- Dual-issue RV64IM processor for fun & learning☆64Updated 2 years ago
- Tool to parse yosys and nextpnr logfiles to then plot LUT, flip-flop and maximum frequency stats as your project progresses.☆22Updated 2 years ago
- Small Processing Unit 32: A compact RV32I CPU written in Verilog☆71Updated 3 years ago
- Minimal DVI / HDMI Framebuffer☆83Updated 5 years ago
- ☆38Updated last year
- ♻️ Convert the NEORV32 processor into a synthesizable plain-Verilog netlist module using GHDL.☆101Updated last month
- Gateware / Firmware / BuildRoot to run linux on iCE40 / iCEBreaker☆103Updated 2 years ago
- Portable HyperRAM controller☆62Updated last year
- USB virtual model in C++ for Verilog☆32Updated last year
- RISC-V Playground on Nandland Go☆16Updated 2 years ago