Alternatives and similar repositories for tinyQV

Users that are interested in tinyQV are comparing it to the libraries listed below

• YosysHQ / setup-oss-cad-suite
  Set up your GitHub Actions workflow with a OSS CAD Suite
  ☆16Updated last year
• chili-chips-ba / openXC7-TetriSaraj
  Demo of how to use https://github.com/openXC7 tools (yosys+nextpnr-xilinx) to implement the HW side of a custom SoC with RISC-V CPU & our…
  ☆26Updated 3 months ago
• meiniKi / FazyRV
  A minimal-area RISC-V core with a scalable data path to 1, 2, 4, or 8 bits and manifold variants.
  ☆93Updated 9 months ago
• jazvw / chip_art
  Convert an image to a GDS format for inclusion in a zerotoasic project
  ☆13Updated 2 years ago
• colognechip / gatemate_ila
  The ILA allows you to perform in-system debugging of your designs on the GateMate FPGA at runtime. All signals of your design inside the …
  ☆51Updated last week
• MichaelBell / nanoV
  RISC-V RV32E core designed for minimal area
  ☆16Updated 6 months ago
• FelipeFFerreira / ITA-CORES
  RISC-V SoC Physical Implementation in 180 nm CMOS with a Quark Core Based on FemtoRV32
  ☆45Updated last year
• TheMightyDuckOfDoom / liberty74
  A Fully Open-Source Verilog-to-PCB Flow
  ☆21Updated 10 months ago
• ecilasun / NekoIchi
  A simple risc-v CPU /GPU running on an Arty A7-100T FPGA board
  ☆29Updated 3 years ago
• fredrequin / verilator_gowin
  Re-coded Gowin GW1N primitives for Verilator use
  ☆18Updated 2 years ago
• Wren6991 / libfpga
  Reusable Verilog 2005 components for FPGA designs
  ☆43Updated 3 months ago
• jeras / rp32
  RISC-V processor with CPI=1 (every single instruction executed in a single clock cycle).
  ☆15Updated last week
• bonfireprocessor / bonfire-cpu
  FPGA optimized RISC-V (RV32IM) implemenation
  ☆34Updated 4 years ago
• nand2mario / ddr3-tang-primer-20k
  DDR3 controller for Tang Primer 20K (Gowin GW2A-18C fpga). DDR3-800 speed and low latency.
  ☆55Updated last year
• GMM-7550 / gmm7550-hardware
  CologneChip GateMate FPGA Module: GMM-7550
  ☆22Updated this week
• olofk / fusesocotb
  Quick'n'dirty FuseSoC+cocotb example
  ☆18Updated 6 months ago
• openXC7 / nextpnr-xilinx
  Experimental flows using nextpnr for Xilinx devices
  ☆47Updated last week
• efabless / caravel_board
  ☆35Updated 6 months ago
• olofk / wb_intercon
  Wishbone interconnect utilities
  ☆41Updated 3 months ago
• tongchen126 / Boot-Debian-On-Litex-Rocket
  ☆13Updated 3 years ago
• YosysHQ / prjpeppercorn
  Project Peppercorn - GateMate FPGA Bitstream Documentation
  ☆21Updated last week
• wyvernSemi / usbModel
  USB virtual model in C++ for Verilog
  ☆30Updated 7 months ago
• efabless / sky130_sram_macros_old
  ☆36Updated 2 years ago
• YosysHQ / padring
  A padring generator for ASICs
  ☆25Updated 2 years ago
• cloudxcc / Arduissimo
  Open source MPSoC running 620 MIPS (CHStone) of RISC-V (RV32iMC) programms on the ARTY board (XC7A35T).
  ☆21Updated 5 years ago
• mole99 / greyhound-ihp
  Greyhound on IHP SG13G2 0.13 μm BiCMOS process
  ☆38Updated 3 weeks ago
• antmicro / topwrap
  A Python package for generating HDL wrappers and top modules for HDL sources
  ☆33Updated 2 weeks ago
• chili-chips-ba / openCologne
  Spicing up the first and (no longer) the only EU FPGA chip with a flashy new board, loaded with a suite of engaging demos and examples =>…
  ☆63Updated last week
• ZiyangYE / General-Slow-DDR3-Interface
  A general slow DDR3 interface. Very little resource consumption. Suits for all FPGAs with 1.5V IO voltage.
  ☆38Updated last year
• mattvenn / multi_project_tools
  tools to help make the most of the limited space we have on the Google sponsored Efabless shuttles
  ☆36Updated 2 years ago