mole99 / greyhound-ihpLinks
Greyhound on IHP SG13G2 0.13 μm BiCMOS process
☆49Updated last month
Alternatives and similar repositories for greyhound-ihp
Users that are interested in greyhound-ihp are comparing it to the libraries listed below
Sorting:
- A minimal-area RISC-V core with a scalable data path to 1, 2, 4, or 8 bits and manifold variants.☆98Updated last week
- Spicing up the first and (no longer) the only EU FPGA chip with a flashy new board, loaded with a suite of engaging demos and examples =>…☆66Updated this week
- SAR ADC on tiny tapeout☆42Updated 6 months ago
- ☆70Updated 11 months ago
- Create fast and efficient standard cell based adders, multipliers and multiply-adders.☆115Updated last year
- A pipelined RISC-V processor☆57Updated last year
- RISC-V Nox core☆66Updated last week
- ASIC implementation flow infrastructure☆58Updated this week
- RISC-V SoC Physical Implementation in 180 nm CMOS with a Quark Core Based on FemtoRV32☆47Updated last year
- SpiceBind – spice inside HDL simulator☆45Updated last month
- submission repository for efabless mpw6 shuttle☆30Updated last year
- An automatic clock gating utility☆50Updated 3 months ago
- ☆32Updated 6 months ago
- ☆54Updated 3 weeks ago
- ☆47Updated 4 months ago
- Experimental flows using nextpnr for Xilinx devices☆49Updated last month
- Prefix tree adder space exploration library☆57Updated 8 months ago
- ☆36Updated 8 months ago
- Convenience script to install the nextpnr-xilinx toolchain for Kintex7, Artix7, Spartan7 and Zynq7☆88Updated last month
- An open-source HDL register code generator fast enough to run in real time.☆72Updated last month
- Open-source RHBD (Radiation Hardened by Design) Standard-Cell Library for SKY130☆8Updated 2 months ago
- Open source designs developed with IHP 130nm BiCMOS Open Source PDK. Documentation at https://ihp-open-ip.readthedocs.io/en/latest/☆54Updated 3 months ago
- A Python package for generating HDL wrappers and top modules for HDL sources☆35Updated this week
- Flip flop setup, hold & metastability explorer tool☆36Updated 2 years ago
- Experimental Tiny Tapeout chip on IHP SG13G2 0.13 μm BiCMOS process☆18Updated 4 months ago
- The ILA allows you to perform in-system debugging of your designs on the GateMate FPGA at runtime. All signals of your design inside the …☆52Updated 2 months ago
- System on Chip toolkit for Amaranth HDL☆92Updated 9 months ago
- A Risc-V SoC for Tiny Tapeout☆30Updated last week
- Single/Multi-channel Full Speed USB interface for FPGA and ASIC designs☆175Updated last year
- BRISKI ( Barrel RISC-V for Kilo-core Implementations ) is a fast and compact RISC-V barrel processor core that emphasize high throughput …☆25Updated 2 months ago