olofk / qerv
☆14Updated 3 months ago
Alternatives and similar repositories for qerv:
Users that are interested in qerv are comparing it to the libraries listed below
- Using VexRiscv without installing Scala☆37Updated 3 years ago
- IEEE 754 single precision floating point library in systemverilog and vhdl☆29Updated 2 months ago
- FPGA based microcomputer sandbox for software and RTL experimentation☆53Updated this week
- ☆59Updated 3 years ago
- RISC-V SoC Physical Implementation in 180 nm CMOS with a Quark Core Based on FemtoRV32☆44Updated last year
- an inverter drawn in magic with makefile to simulate☆26Updated 2 years ago
- Convenience script to install the nextpnr-xilinx toolchain for Kintex7, Artix7, Spartan7 and Zynq7☆67Updated 8 months ago
- Reusable Verilog 2005 components for FPGA designs☆40Updated 2 weeks ago
- A pipelined RISC-V processor☆51Updated last year
- Wishbone interconnect utilities☆38Updated last month
- A minimal-area RISC-V core with a scalable data path to 1, 2, 4, or 8 bits and manifold variants.☆89Updated 6 months ago
- FPGA IP cores for the Antikernel OS, intended to be included as a submodule in SoC integrations☆62Updated 2 weeks ago
- PicoRV☆44Updated 5 years ago
- Spicing up the first and (no longer) the only EU FPGA chip with a flashy new board, loaded with a suite of engaging demos and examples =>…☆58Updated this week
- The ILA allows you to perform in-system debugging of your designs on the GateMate FPGA at runtime. All signals of your design inside the …☆50Updated last month
- Fully featured implementation of Inter-IC (I2C) bus master for FPGAs☆26Updated 4 years ago
- A Python package for generating HDL wrappers and top modules for HDL sources☆31Updated last week
- USB virtual model in C++ for Verilog☆29Updated 4 months ago
- FPGA250 aboard the eFabless Caravel☆29Updated 4 years ago
- Constraint files for Hardware Description Language (HDL) designs targeting FPGA boards☆43Updated last week
- Bitstream relocation and manipulation tool.☆43Updated 2 years ago
- Generate Zynq configurations without using the vendor GUI☆30Updated last year
- RISC-V Processor written in Amaranth HDL☆36Updated 3 years ago
- ☆66Updated 6 months ago
- Example Verilog code for Ulx3s☆40Updated 2 years ago
- Dual-issue RV64IM processor for fun & learning☆57Updated last year
- Another size-optimized RISC-V CPU for your consideration.☆59Updated last week
- Basic USB 1.1 Host Controller for small FPGAs☆88Updated 4 years ago
- A collection of debugging busses developed and presented at zipcpu.com☆37Updated last year
- 🔥 Technology-agnostic FPGA stress-test: maximum logic utilization and high dynamic power consumption.☆29Updated 2 years ago