Alternatives and similar repositories for qerv:

Users that are interested in qerv are comparing it to the libraries listed below

• Wren6991 / libfpga
  Reusable Verilog 2005 components for FPGA designs
  ☆42Updated 2 months ago
• taneroksuz / fpu-sp
  IEEE 754 single precision floating point library in systemverilog and vhdl
  ☆29Updated 4 months ago
• BrunoLevy / TordBoyau
  A pipelined RISC-V processor
  ☆55Updated last year
• lawrie / ulx3s_examples
  Example Verilog code for Ulx3s
  ☆40Updated 3 years ago
• meiniKi / FazyRV
  A minimal-area RISC-V core with a scalable data path to 1, 2, 4, or 8 bits and manifold variants.
  ☆91Updated 8 months ago
• hdl-util / i2c
  Fully featured implementation of Inter-IC (I2C) bus master for FPGAs
  ☆27Updated 4 years ago
• clairexen / picorv
  PicoRV
  ☆44Updated 5 years ago
• epsilon537 / boxlambda
  FPGA based microcomputer sandbox for software and RTL experimentation
  ☆55Updated this week
• mattvenn / magic-inverter
  an inverter drawn in magic with makefile to simulate
  ☆26Updated 2 years ago
• m-labs / VexRiscv-verilog
  Using VexRiscv without installing Scala
  ☆38Updated 3 years ago
• FelipeFFerreira / ITA-CORES
  RISC-V SoC Physical Implementation in 180 nm CMOS with a Quark Core Based on FemtoRV32
  ☆45Updated last year
• olofk / wb_intercon
  Wishbone interconnect utilities
  ☆41Updated 3 months ago
• openXC7 / toolchain-installer
  Convenience script to install the nextpnr-xilinx toolchain for Kintex7, Artix7, Spartan7 and Zynq7
  ☆72Updated 10 months ago
• pulp-platform / pulp-ethernet
  ☆14Updated last month
• cr1901 / sentinel
  Another size-optimized RISC-V CPU for your consideration.
  ☆58Updated this week
• fontamsoc / pu32
  ☆15Updated last year
• zephray / RISu064
  Dual-issue RV64IM processor for fun & learning
  ☆60Updated last year
• mole99 / greyhound-ihp
  Greyhound on IHP SG13G2 0.13 μm BiCMOS process
  ☆28Updated 3 weeks ago
• olofk / subservient
  Small SERV-based SoC primarily for OpenMPW tapeout
  ☆42Updated 4 months ago
• stnolting / neorv32-riscof
  ✔️ Port of RISCOF to check the NEORV32 for RISC-V ISA compatibility.
  ☆33Updated this week
• blackmesalabs / hyperram
  Portable Verilog RTL interface to S27KL0641DABHI020 64Mbit HyperRAM IC
  ☆86Updated 6 years ago
• aignacio / mpsoc_example
  ☆59Updated 3 years ago
• dovebutch / tlv-comp
  ☆27Updated 2 months ago
• colognechip / gatemate_ila
  The ILA allows you to perform in-system debugging of your designs on the GateMate FPGA at runtime. All signals of your design inside the …
  ☆50Updated 3 months ago
• ZipCPU / dbgbus
  A collection of debugging busses developed and presented at zipcpu.com
  ☆41Updated last year
• ZipCPU / s6soc
  CMod-S6 SoC
  ☆40Updated 7 years ago
• mattvenn / gtkwave-python-filter-process
  ☆33Updated 4 years ago
• ZipCPU / qoiimg
  Quite OK image compression Verilog implementation
  ☆21Updated 5 months ago
• olofk / vidbo
  Virtual Development Board
  ☆59Updated 3 years ago
• ChrisPVille / jtaglet
  Easy-to-use JTAG TAP and Debug Controller core written in Verilog
  ☆28Updated 6 years ago