APB Logic
☆26Jun 29, 2026Updated this week
Alternatives and similar repositories for apb
Users that are interested in apb are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- ☆23Feb 22, 2020Updated 6 years ago
- Sphinx domain to allow integration of Verilog / SystemVerilog documentation into Sphinx.☆27Mar 1, 2021Updated 5 years ago
- ☆10Apr 8, 2021Updated 5 years ago
- Parametric GPIO Peripheral☆13Jan 30, 2025Updated last year
- FPGA Low latency 10GBASE-R PCS☆13May 23, 2023Updated 3 years ago
- GPUs on demand by Runpod - Special Offer Available • AdRun AI, ML, and HPC workloads on powerful cloud GPUs—without limits or wasted spend. Deploy GPUs in under a minute and pay by the second.
- ☆40Jun 13, 2015Updated 11 years ago
- Wrapper shells enabling designs generated by rocket-chip to map onto certain FPGA boards☆20Nov 27, 2024Updated last year
- Skid Buffer and Pipeline Skid Buffer designed in Verilog/System Verilog.☆33Nov 3, 2025Updated 7 months ago
- Improved version of http://web.mit.edu/6.111/volume2/www/f2018/tools/sd_controller.v☆13Dec 6, 2021Updated 4 years ago
- Latest in the line of the E32 processors with better/generic cache placement☆10Feb 25, 2023Updated 3 years ago
- Fully featured implementation of Inter-IC (I2C) bus master for FPGAs☆34May 17, 2020Updated 6 years ago
- SystemVerilog modules and classes commonly used for verification☆57Jan 5, 2026Updated 5 months ago
- Benchmarks for High-Level Synthesis☆11Mar 17, 2023Updated 3 years ago
- HeteroGen: transpiling C to heterogeneous HLS code with automated test generation and program repair (ASPLOS 2022)☆16Sep 25, 2024Updated last year
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click. Zero configuration with optimized deployments.
- 💵 A simple expense tracker app created using MVVM architecture pattern. Built using Android-Jetpack Compose and Room.☆10May 5, 2026Updated last month
- ☆25Oct 8, 2019Updated 6 years ago
- OBI SystemVerilog synthesizable interconnect IPs for on-chip communication☆20Jun 16, 2026Updated last week
- CSC403: Computer Organization and Architecture [COA] & CSL403: Processor Architecture Lab [PAL] | SE Semester IV | Computer Engineering☆21Feb 20, 2026Updated 4 months ago
- AHB-lite, AHB-APB bridge and extended APB side architecture in SystemVerilog☆20Sep 2, 2023Updated 2 years ago
- ☆16May 6, 2026Updated last month
- MICRO 2024 Evaluation Artifact for FuseMax☆17Aug 26, 2024Updated last year
- 最小和算法实现☆10Jul 12, 2020Updated 5 years ago
- ☆18Jul 9, 2025Updated 11 months ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- General Purpose IO with APB4 interface☆16May 10, 2024Updated 2 years ago
- A mock framework for use with SVUnit☆19Jun 27, 2023Updated 3 years ago
- Simple single-port AXI memory interface☆50Jun 7, 2024Updated 2 years ago
- ☆21Dec 9, 2018Updated 7 years ago
- A lightweight Ethernet MAC Controller IP for FPGA prototyping☆14Oct 19, 2020Updated 5 years ago
- ☆14Jul 5, 2019Updated 6 years ago
- Simple and effective parallel CRC calculator written in synthesizable SystemVerilog☆15Apr 11, 2019Updated 7 years ago
- A simple spidergon network-on-chip with wormhole switching feature☆12Mar 22, 2021Updated 5 years ago
- SpinalHDL USB system for the ULPI based Arrow DECA board☆20Jan 9, 2022Updated 4 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- ☆50Mar 31, 2026Updated 2 months ago
- spike-vp☆13Feb 5, 2024Updated 2 years ago
- This is a series of quick start guide of Vitis HLS tool in Chinese. It explains the basic concepts and the most important optimize techni…☆25Nov 9, 2022Updated 3 years ago
- SystemVerilog overhaul of ESP L2 and LLC caches with directory based protocol☆19Feb 27, 2025Updated last year
- A modular, parametrizable, and highly flexible Data Movement Accelerator (DMA)☆219Updated this week
- 关于深度学习算法、框架、编译器、加速器的一些理解☆16Jul 2, 2022Updated 3 years ago
- The repo contains the SPMP architectural specification, which includes capabilities like access control of read/write/execute requests by…☆23Jun 22, 2026Updated last week