pulp-platform / apbLinks
APB Logic
☆18Updated 6 months ago
Alternatives and similar repositories for apb
Users that are interested in apb are comparing it to the libraries listed below
Sorting:
- SystemVerilog IPs and Modules for architectural redundancy designs.☆14Updated last week
- ☆20Updated 5 years ago
- Skid Buffer and Pipeline Skid Buffer designed in Verilog/System Verilog.☆19Updated 10 months ago
- ☆30Updated 2 months ago
- A 32 bit RISCV Based SOC with QSpi , Uart and 8 bit SDRAM Controller tagetted to efebless shuttle program☆20Updated 2 years ago
- ☆21Updated 5 years ago
- Simple single-port AXI memory interface☆41Updated last year
- WISHBONE DMA/Bridge IP Core☆18Updated 10 years ago
- Common SystemVerilog RTL modules for RgGen☆13Updated 3 weeks ago
- Andes Vector Extension support added to riscv-dv☆17Updated 5 years ago
- DUTH RISC-V Superscalar Microprocessor☆31Updated 8 months ago
- Constrained RAndom Verification Enviroment (CRAVE)☆17Updated last year
- RISC-V soft-core PEs for TaPaSCo☆21Updated last year
- Neural Network accelerator powered by MVUs and RISC-V.☆13Updated 11 months ago
- YosysHQ SVA AXI Properties☆40Updated 2 years ago
- verification of simple axi-based cache☆18Updated 6 years ago
- Reconfigurable Binary Engine☆17Updated 4 years ago
- Network on Chip for MPSoC☆26Updated last month
- SystemVerilog Functional Coverage for RISC-V ISA☆28Updated 3 weeks ago
- A barebones 64-bit RISC-V micro-controller class CPU, implementing the I(nteger), M(ul/div), C(ompressed) and K(ryptography) extensions.☆44Updated 3 years ago
- SoC Based on ARM Cortex-M3☆32Updated last month
- APB UVC ported to Verilator☆11Updated last year
- Multi-Processor System on Chip verified with UVM/OSVVM/FV☆31Updated last month
- RISC-V Rocket Chip Strap-on-Booster with Fused Universal Neural Network (FuNN) eNNgine☆22Updated 3 years ago
- Platform Level Interrupt Controller☆41Updated last year
- ☆26Updated 4 years ago
- RISCV core RV32I/E.4 threads in a ring architecture☆32Updated 2 years ago
- Accelerating the AES algorithm on an FPGA and comparing the speedup with both AES and Modified AES algorithms☆27Updated 3 years ago
- Implementation of a binary search tree algorithm in a FPGA/ASIC IP☆19Updated 3 years ago
- SystemVerilog Logger☆18Updated 2 years ago