APB Logic
☆24Feb 24, 2026Updated last month
Alternatives and similar repositories for apb
Users that are interested in apb are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- ☆22Feb 22, 2020Updated 6 years ago
- ☆10Apr 8, 2021Updated 5 years ago
- Parametric GPIO Peripheral☆12Jan 30, 2025Updated last year
- FPGA Low latency 10GBASE-R PCS☆12May 23, 2023Updated 2 years ago
- ☆40Jun 13, 2015Updated 10 years ago
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting with the flexibility to host WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Cloudways by DigitalOcean.
- Wrapper shells enabling designs generated by rocket-chip to map onto certain FPGA boards☆20Nov 27, 2024Updated last year
- Sphinx domain to allow integration of Verilog / SystemVerilog documentation into Sphinx.☆26Mar 1, 2021Updated 5 years ago
- Skid Buffer and Pipeline Skid Buffer designed in Verilog/System Verilog.☆31Nov 3, 2025Updated 5 months ago
- Improved version of http://web.mit.edu/6.111/volume2/www/f2018/tools/sd_controller.v☆13Dec 6, 2021Updated 4 years ago
- Latest in the line of the E32 processors with better/generic cache placement☆10Feb 25, 2023Updated 3 years ago
- Fully featured implementation of Inter-IC (I2C) bus master for FPGAs☆33May 17, 2020Updated 5 years ago
- Benchmarks for High-Level Synthesis☆10Mar 17, 2023Updated 3 years ago
- SystemVerilog modules and classes commonly used for verification☆57Jan 5, 2026Updated 3 months ago
- HeteroGen: transpiling C to heterogeneous HLS code with automated test generation and program repair (ASPLOS 2022)☆16Sep 25, 2024Updated last year
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting with the flexibility to host WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Cloudways by DigitalOcean.
- 💵 A simple expense tracker app created using MVVM architecture pattern. Built using Android-Jetpack Compose and Room.☆10Jul 7, 2023Updated 2 years ago
- ☆24Oct 8, 2019Updated 6 years ago
- AHB-lite, AHB-APB bridge and extended APB side architecture in SystemVerilog☆18Sep 2, 2023Updated 2 years ago
- OBI SystemVerilog synthesizable interconnect IPs for on-chip communication☆19Jan 9, 2026Updated 3 months ago
- CSC403: Computer Organization and Architecture [COA] & CSL403: Processor Architecture Lab [PAL] | SE Semester IV | Computer Engineering☆19Feb 20, 2026Updated last month
- MICRO 2024 Evaluation Artifact for FuseMax☆17Aug 26, 2024Updated last year
- ☆15Mar 9, 2026Updated last month
- 最小和算法实现☆10Jul 12, 2020Updated 5 years ago
- A mock framework for use with SVUnit☆19Jun 27, 2023Updated 2 years ago
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click and start building anything your business needs.
- ☆18Jul 9, 2025Updated 9 months ago
- General Purpose IO with APB4 interface☆15May 10, 2024Updated last year
- Simple single-port AXI memory interface☆49Jun 7, 2024Updated last year
- ☆21Dec 9, 2018Updated 7 years ago
- A lightweight Ethernet MAC Controller IP for FPGA prototyping☆14Oct 19, 2020Updated 5 years ago
- Simple and effective parallel CRC calculator written in synthesizable SystemVerilog☆15Apr 11, 2019Updated 6 years ago
- ☆14Jul 5, 2019Updated 6 years ago
- A simple spidergon network-on-chip with wormhole switching feature☆12Mar 22, 2021Updated 5 years ago
- SpinalHDL USB system for the ULPI based Arrow DECA board☆20Jan 9, 2022Updated 4 years ago
- Proton VPN Special Offer - Get 70% off • AdSpecial partner offer. Trusted by over 100 million users worldwide. Tested, Approved and Recommended by Experts.
- spike-vp☆13Feb 5, 2024Updated 2 years ago
- ☆47Mar 31, 2026Updated last week
- This is a series of quick start guide of Vitis HLS tool in Chinese. It explains the basic concepts and the most important optimize techni…☆26Nov 9, 2022Updated 3 years ago
- A modular, parametrizable, and highly flexible Data Movement Accelerator (DMA)☆202Mar 6, 2026Updated last month
- SystemVerilog overhaul of ESP L2 and LLC caches with directory based protocol☆18Feb 27, 2025Updated last year
- 关于深度学习算法、框架、编译器、加速器的一些理解☆16Jul 2, 2022Updated 3 years ago
- Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.☆19Feb 25, 2026Updated last month