ngiambla / libmemLinks
☆10Updated 2 years ago
Alternatives and similar repositories for libmem
Users that are interested in libmem are comparing it to the libraries listed below
Sorting:
- Benchmarks, testbenches, and transformed codes for high-level synthesis research☆13Updated 7 years ago
- TAPA is a dataflow HLS framework that features fast compilation, expressive programming model and generates high-frequency FPGA accelerat…☆19Updated 10 months ago
- SmartNIC☆14Updated 6 years ago
- PAAS: A System Level Simulator for Heterogeneous (CPU-FPGA) Computing Systems☆43Updated 3 years ago
- Hi-DMM: High-Performance Dynamic Memory Management in HLS (High-Level Synthesis)☆25Updated 6 years ago
- Hybrid BFS on Xilinx Zynq☆18Updated 10 years ago
- Networking Template Library for Vivado HLS☆28Updated 5 years ago
- FleetRec: Large-Scale Recommendation Inference on Hybrid GPU-FPGA Clusters☆16Updated 4 years ago
- Tutorial Material from the SST Team☆21Updated last month
- HeteroGen: transpiling C to heterogeneous HLS code with automated test generation and program repair (ASPLOS 2022)☆17Updated 9 months ago
- P4 compatible HLS modules☆11Updated 7 years ago
- Benchmark suite containing cache filtered traces for use with Ramulator. These include some of the workloads used in our SIGMETRICS 2019 …☆22Updated 4 years ago
- corundum work on vu13p☆19Updated last year
- ☆33Updated 4 years ago
- ☆13Updated 3 years ago
- ☆19Updated 4 years ago
- A simple MIPS-like CPU demo in C++ for Xilinx Vivado HLS☆18Updated 6 years ago
- Domain-Specific Architecture Generator 2☆21Updated 2 years ago
- ☆13Updated 3 years ago
- Checksum plays a key role in the TCP/IP headers. In this repo you'll find a efficient FPGA-based solution for a 512-bit AXI4-Stream inter…☆18Updated 5 years ago
- Dynamically Reconfigurable Architecture Template and Cycle-level Microarchitecture Simulator for Dataflow AcCelerators☆28Updated 2 years ago
- OPAE porting to Xilinx FPGA devices.☆39Updated 4 years ago
- Netrace: a network packet trace reader☆13Updated 11 years ago
- Heterogeneous Accelerated Computed Cluster (HACC) Resources Page☆21Updated last month
- An example of using Ramulator as memory model in a cycle-accurate SystemC Design☆51Updated 8 years ago
- Source code for the architectural and circuit-level simulators used for modeling the CROW (Copy-ROW DRAM) mechanism proposed in our ISCA …☆15Updated 5 years ago
- Replace original DRAM model in GPGPU-sim with Ramulator DRAM model☆18Updated 6 years ago
- High Bandwidth Memory (HBM) timing model based on DRAMSim2☆42Updated 7 years ago
- TensorCore Vector Processor for Deep Learning - Google Summer of Code Project☆22Updated 3 years ago
- ☆24Updated 4 years ago