Alternatives and similar repositories for libmem:

Users that are interested in libmem are comparing it to the libraries listed below

• Junyi-Liu / benchmarks-HLS
  Benchmarks, testbenches, and transformed codes for high-level synthesis research
  ☆13Updated 7 years ago
• zslwyuan / PAAS_V1.0
  PAAS: A System Level Simulator for Heterogeneous (CPU-FPGA) Computing Systems
  ☆43Updated 3 years ago
• maltanar / fpga-booleanring-bfs
  Hybrid BFS on Xilinx Zynq
  ☆18Updated 9 years ago
• Xilinx / hydra
  ☆12Updated 2 years ago
• acsl-technion / ntl
  Networking Template Library for Vivado HLS
  ☆28Updated 4 years ago
• bespoke-silicon-group / bsg_bladerunner
  Meta-Repository for Bespoke Silicon Group's Manycore Architecture (A.K.A HammerBlade)
  ☆38Updated last month
• fpgasystems / GPU-FPGA-Recommendation-System
  FleetRec: Large-Scale Recommendation Inference on Hybrid GPU-FPGA Clusters
  ☆16Updated 3 years ago
• template-hls / template-hls-float
  ☆27Updated 5 years ago
• Blaok / tapa
  TAPA is a dataflow HLS framework that features fast compilation, expressive programming model and generates high-frequency FPGA accelerat…
  ☆19Updated 4 months ago
• engjefersonsantiago / P4HLS
  P4 compatible HLS modules
  ☆10Updated 6 years ago
• PrincetonUniversity / primesim
  A parallel and distributed simulator for thousand-core chips
  ☆22Updated 6 years ago
• StanfordAHA / CGRAFlowDoc
  Documentation for the entire CGRAFlow
  ☆19Updated 3 years ago
• GramThanos / CPU-on-Vivado-HLS
  A simple MIPS-like CPU demo in C++ for Xilinx Vivado HLS
  ☆18Updated 5 years ago
• ucb-ee290c / fa18-smartnic
  SmartNIC
  ☆14Updated 6 years ago
• maswx / vu13p_corundum
  corundum work on vu13p
  ☆18Updated last year
• OSU-STARLAB / GPGPU-Ramulator-Simulator
  Replace original DRAM model in GPGPU-sim with Ramulator DRAM model
  ☆17Updated 6 years ago
• MPSLab-ASU / DiRAC
  Dynamically Reconfigurable Architecture Template and Cycle-level Microarchitecture Simulator for Dataflow AcCelerators
  ☆28Updated last year
• Reconfigurable-Computing / HLStoFPGA
  ☆12Updated 2 years ago
• zslwyuan / Hi-DMM
  Hi-DMM: High-Performance Dynamic Memory Management in HLS (High-Level Synthesis)
  ☆25Updated 6 years ago
• PolyArch / dsagen2
  Domain-Specific Architecture Generator 2
  ☆21Updated 2 years ago
• UCLA-VAST / heterohalide
  HeteroHalide: From Image Processing DSL to Efficient FPGA Acceleration
  ☆15Updated 4 years ago
• UCLA-VAST / hbmbench
  ☆23Updated 4 years ago
• pgroupATusc / fasthash
  Source Code for the paper Titled FASTHash: FPGA-Based High Throughput Parallel Hash Table published in ISC high performance 2020
  ☆20Updated 2 years ago
• jianyicheng / HLS-benchmarks
  Benchmarks for High-Level Synthesis
  ☆10Updated last year
• TonyBrewer / OpenHT
  Hybrid Threading Tool Set
  ☆15Updated 4 years ago
• maltanar / spmvaccsim
  A SystemC + DRAMSim2 simulator for exploring the SpMV hardware accelerator design space.
  ☆14Updated 10 years ago
• hyoukjun / microswitch-noc
  ☆24Updated 5 years ago
• natu4u / GSOC_TensorCore
  TensorCore Vector Processor for Deep Learning - Google Summer of Code Project
  ☆21Updated 3 years ago
• IronySuzumiya / NiuDianNao
  A simple cycle-accurate DaDianNao simulator
  ☆13Updated 5 years ago
• sstsimulator / sst-tutorials
  Tutorial Material from the SST Team
  ☆18Updated 8 months ago