Alternatives and similar repositories for byoc

Users that are interested in byoc are comparing it to the libraries listed below

• seldridge / rocket-rocc-examples
  Tests for example Rocket Custom Coprocessors
  ☆75Updated 5 years ago
• CMU-SAFARI / PiDRAM
  PiDRAM is the first flexible end-to-end framework that enables system integration studies and evaluation of real Processing-using-Memory …
  ☆70Updated 2 years ago
• lana555 / dynamatic
  ☆87Updated last year
• cwfletcher / buffets
  Implementations of Buffets, which are efficient, composable idioms for implementing Explicit Decoupled Data Orchestration.
  ☆81Updated 6 years ago
• breagen / MachSuite
  Benchmarks for Accelerator Design and Customized Architectures
  ☆135Updated 5 years ago
• sld-columbia / hl5
  A 32-bit RISC-V Processor Designed with High-Level Synthesis
  ☆54Updated 5 years ago
• zslwyuan / PAAS_V1.0
  PAAS: A System Level Simulator for Heterogeneous (CPU-FPGA) Computing Systems
  ☆43Updated 4 years ago
• TeCSAR-UNCC / gem5-SALAM
  ☆108Updated last year
• StanfordAHA / garnet
  Next generation CGRA generator
  ☆118Updated last week
• tancheng / VectorCGRA
  CGRA framework with vectorization support.
  ☆42Updated this week
• StanfordAHA / aha
  ☆62Updated 2 weeks ago
• esa-tu-darmstadt / tapasco
  The Task Parallel System Composer (TaPaSCo)
  ☆115Updated last week
• MPSLab-ASU / ccf
  CGRA Compilation Framework
  ☆89Updated 2 years ago
• ucb-bar / sha3
  ☆82Updated last year
• meton-robean / Vector_MulAdd_Accelerator
  vector multiplication adder accelerator (using chisel 3 and RocketChip RoCC ) 向量乘法累加加速器
  ☆53Updated 5 years ago
• tancheng / CGRA-Flow
  CGRA-Flow is an integrated framework for CGRA compilation, exploration, synthesis, and development.
  ☆149Updated this week
• pulp-platform / hero
  Heterogeneous Research Platform (HERO) for exploration of heterogeneous computers consisting of programmable many-core accelerators and a…
  ☆114Updated 2 years ago
• UCLA-VAST / AutoBridge
  [FPGA 2021, Best Paper Award] An automated floorplanning and pipelining tool for Vivado HLS.
  ☆127Updated 2 years ago
• tancheng / CGRA-Mapper
  An LLVM pass that can generate CDFG and map the target loops onto a parameterizable CGRA.
  ☆79Updated last week
• Xilinx / merlin-compiler
  ☆60Updated 2 years ago
• RALC88 / riscv-vectorized-benchmark-suite
  RiVEC Bencmark Suite
  ☆126Updated last year
• li3tuo4 / rc-fpga-zcu
  Port fpga-zynq (rocket-chip) to Xilinx ZYNQ Ultrascale+ board (ZCU102)
  ☆64Updated 2 years ago
• stillwater-sc / RISC-V-TensorCore
  Transactional Verilog design and Verilator Testbench for a RISC-V TensorCore Vector co-processor for reproducible linear algebra
  ☆62Updated 4 years ago
• jianyicheng / DSS
  DASS HLS Compiler
  ☆29Updated 2 years ago
• ucb-bar / gemmini-rocc-tests
  Fork of seldridge/rocket-rocc-examples with tests for a systolic array based matmul accelerator
  ☆61Updated 6 months ago
• circt-hls / circt-hls
  CIRCT-based HLS compilation flows, debugging, and cosimulation tools.
  ☆53Updated 2 years ago
• MPSLab-ASU / DiRAC
  Dynamically Reconfigurable Architecture Template and Cycle-level Microarchitecture Simulator for Dataflow AcCelerators
  ☆30Updated 2 years ago
• tukl-msd / gem5.TnT
  gem5 Tips & Tricks
  ☆70Updated 5 years ago
• zslwyuan / Light-HLS
  Fast, Accurate and Convenient Light-Weight HLS Framework for Academic Design Space Exploration and Evaluation. (LLVM-11)
  ☆62Updated 3 years ago
• ccelio / chisel-style-guide
  A Style Guide for the Chisel Hardware Construction Language
  ☆108Updated 4 years ago