compsec-snu / specdoctor
☆19Updated last year
Related projects ⓘ
Alternatives and complementary repositories for specdoctor
- ☆74Updated 5 months ago
- Proof of concept code for the BranchSpec exploit.☆9Updated 2 years ago
- ☆18Updated 2 years ago
- Streamline Covert Channel Attack (presented in ASPLOS'21)☆19Updated 3 years ago
- The artifact for SecSMT paper -- Usenix Security 2022☆25Updated 2 years ago
- ☆34Updated 3 years ago
- Gem5 implementation of "InvisiSpec", a defense mechanism of speculative execution attacks on cache hierarchy.☆58Updated 4 years ago
- Data-centric defense mechanism against Spectre attacks. (DAC'19)☆11Updated 5 years ago
- A behavioural cache model for analysing the cache behaviour under side-channel attack.☆22Updated last month
- CleanupSpec (MICRO-2019)☆17Updated 4 years ago
- Security Test Benchmark for Computer Architectures☆20Updated this week
- HW interface for memory caches☆26Updated 4 years ago
- Medusa Repository: Transynther tool and Medusa Attack☆18Updated 4 years ago
- Proof-of-concept implementation for the paper "A Security RISC: Microarchitectural Attacks on Hardware RISC-V CPUs" (IEEE S&P 2023)☆54Updated 3 months ago
- Hands on with side-channels: a tutorial on covert-channels built using shared CPU resources. Three different covert-channel implementatio…☆42Updated 5 years ago
- The open-source component of Prime+Scope, published at CCS 2021☆27Updated last year
- New Cache implementation using Gem5☆13Updated 10 years ago
- ☆17Updated 2 years ago
- This repository contains the hardware, software, and OS support for the Programmable Hardware Monitor (PHMon).☆25Updated 4 years ago
- Reload+Refresh PoC☆13Updated 4 years ago
- Artifact evaluation of paper: MorFuzz: Fuzzing Processor via Runtime Instruction Morphing enhanced Synchronizable Co-simulation☆23Updated 10 months ago
- Microarchitectural attack development frameworks for prototyping attacks in native code (C, C++, ASM) and in the browser☆60Updated 2 years ago
- Library for Prime+Probe cache side-channel attacks on L1 and L2☆27Updated 4 years ago
- A port of the RIPE suite to RISC-V.☆28Updated 6 years ago
- Proof-of-concept implementation for the paper "Osiris: Automated Discovery of Microarchitectural Side Channels" (USENIX Security'21)☆54Updated 2 years ago
- Proof-of-concept for I See Dead Micro-Ops transient execution attack☆14Updated 3 years ago
- ☆18Updated 6 years ago
- MIRAGE (USENIX Security 2021)☆11Updated last year
- This repository provides Pensieve, a security evaluation framework for microarchitectural defenses against speculative execution attacks.☆18Updated 10 months ago
- GPU-enabled Hardware Fuzzer using Genetic Algorithm☆16Updated last year