Alternatives and similar repositories for gem5-fs-handbook

Users that are interested in gem5-fs-handbook are comparing it to the libraries listed below

• ConvolutedDog / gpgpu-sim-comments
  GPGPU-Sim 中文注释版代码，包含 GPGPU-Sim 模拟器的最新版代码，经过中文注释，以帮助中文用户更好地理解和使用该模拟器。
  ☆26Updated 10 months ago
• arch-simulator-sig / simulator-paper
  ☆11Updated last year
• cry-daniel / Computer-Architecture-Learning
  ☆65Updated 2 years ago
• lshpku / hwd-prefetch-study
  A Study of the SiFive Inclusive L2 Cache
  ☆69Updated last year
• shinezyy / gem5_data_proc
  data preprocessing scripts for gem5 output
  ☆19Updated 5 months ago
• baichen318 / arch-explorer
  ArchExplorer: Microarchitecture Exploration Via Bottleneck Analysis
  ☆34Updated last year
• qiyancos / gem5-with-chinese-comment
  Gem5 with chinese comment and introduction (master) and some other std gem5 version.
  ☆42Updated 3 years ago
• agusnt / Berti-Artifact
  An artifact for Berti: an Accurate and Timely Local-Delta Data Prefetcher
  ☆35Updated 3 years ago
• lizhirui / DreamCoreV2
  ☆22Updated 2 years ago
• THU-DSP-LAB / ventus-gpgpu-cpp-simulator
  Cycle-accurate C++ & SystemC simulator for the RISC-V GPGPU Ventus
  ☆29Updated this week
• zeal4u / PMP
  About the source code of "Merging Similar Patterns for Hardware Prefetching" paper, which is accepted in MICRO 2022.
  ☆14Updated 2 years ago
• OpenXiangShan / GEM5
  ☆112Updated this week
• ucb-bar / virgo
  Cluster-level matrix unit integration into GPUs, implemented in Chipyard SoC
  ☆43Updated 5 months ago
• CMU-SAFARI / Hermes
  A speculative mechanism to accelerate long-latency off-chip load requests by removing on-chip cache access latency from their critical pa…
  ☆76Updated 2 months ago
• miaochenlu / Gem5_tutorials
  ☆22Updated last week
• Jpz-sdju / trinity
  ☆31Updated 3 months ago
• tukl-msd / gem5.TnT
  gem5 Tips & Tricks
  ☆70Updated 5 years ago
• suchandler96 / gem5-NVDLA
  ☆36Updated 7 months ago
• casys-kaist / mNPUsim
  mNPUsim: A Cycle-accurate Multi-core NPU Simulator (IISWC 2023)
  ☆65Updated 2 weeks ago
• yonseicasl / NPUsim
  NPUsim: Full-Model, Cycle-Level, and Value-Aware Simulator for DNN Accelerators
  ☆44Updated 10 months ago
• CMU-SAFARI / Pythia-HDL
  Implementation of Pythia: A Customizable Hardware Prefetching Framework Using Online Reinforcement Learning in Chisel HDL. To know more, …
  ☆17Updated 4 years ago
• eric-rotenberg / CVP
  Championship Value Prediction (CVP) simulator.
  ☆17Updated 4 years ago
• schoeberl / chisel-empty
  An almost empty chisel project as a starting point for hardware design
  ☆33Updated 9 months ago
• TeCSAR-UNCC / gem5-SALAM
  ☆105Updated last year
• gem5 / gem5-resources
  The official repository for the gem5 resources sources.
  ☆73Updated last week
• car3s / IPCP_ISCA2020
  Source codes for "Bouquet of Instruction Pointers"
  ☆17Updated 5 years ago
• stillwater-sc / RISC-V-TensorCore
  Transactional Verilog design and Verilator Testbench for a RISC-V TensorCore Vector co-processor for reproducible linear algebra
  ☆57Updated 3 years ago
• wshenyi / EECS-470-FinalProject
  A 2-Way Super-Scalar OoO RISC-V Core Based on Intel P6 Microarchitecture.
  ☆15Updated 3 years ago
• miaochenlu / learn_prefetcher
  hardware & software prefetcher
  ☆29Updated last year
• lshpku / gem5-runahead
  Implementing the Precise Runahead (HPCA'20) in gem5
  ☆13Updated 2 years ago