Alternatives and similar repositories for riscv-tests-am

Users that are interested in riscv-tests-am are comparing it to the libraries listed below

• ysyx-ta / ysyx-summer-readings
  ☆66Updated 11 months ago
• MrAMS / Nagi
  基于difftest改进的CPU敏捷开发框架（龙芯杯2024）
  ☆23Updated 10 months ago
• MrAMS / NagiCore
  顺序单/双发射LA32R处理器 (龙芯杯2024) A LA32R CPU in chisel
  ☆23Updated 8 months ago
• arch-simulator-sig / advanced-computer-architecture
  体系结构研讨 + ysyx高阶大纲 (WIP
  ☆172Updated 9 months ago
• oscc-web / ysyx-website
  The official website of One Student One Chip project.
  ☆10Updated last week
• OSCPU / yosys-sta
  ☆73Updated 2 months ago
• OSCPU / chisel-playground
  ☆67Updated 5 months ago
• OSCPU / ysyx-exam
  ☆21Updated last year
• OpenXiangShan / difftest
  Modern co-simulation framework for RISC-V CPUs
  ☆147Updated last week
• OSCPU / ysyxSoC
  ☆86Updated 2 months ago
• cyyself / soc-simulator
  A Verilator based SoC simulator that allows you to define AXI Slave interface in software.
  ☆49Updated 8 months ago
• OpenXiangShan / gsim
  ☆40Updated this week
• Clo91eaf / PUA-MIPS
  NSCSCC 2023 The Second Prize. TEAM PUA FROM HDU.
  ☆13Updated 3 months ago
• OpenXiangShan / XiangShan-Design-Doc
  Documentation for XiangShan Design
  ☆29Updated this week
• fluctlight001 / Generic-Cache-Module
  适用于龙芯杯团队赛入门选手的应急cache模块
  ☆28Updated last year
• CmdBlockZQG / rvcore-mini-linux
  Build mini linux for your own RISC-V emulator!
  ☆21Updated 10 months ago
• sycuricon / starship
  Run rocket-chip on FPGA
  ☆68Updated 8 months ago
• OSCPU-Zhoushan / Zhoushan
  Open Source Chip Project by University (OSCPU) - Zhoushan Core
  ☆51Updated 2 years ago
• ftppz / ShanghaiTech-YSYX
  Unofficial guide for ysyx students applying to ShanghaiTech University
  ☆21Updated 4 months ago
• secure-v / vsh
  VSH（SHell for Visualizing vcd file）项目为数字波形文件命令行查看器。
  ☆20Updated 2 weeks ago
• NoAXI / NoAXI-LoongArch-CPU
  Second Prize in NSCSCC 2024. Developed by team NoAXI from Hangzhou Dianzi University.
  ☆17Updated 10 months ago
• FurryAcetylCoA / gtkwave-filter-process-RISC
  A tool to decode RISC-V and LoongArch and MIPS instructions in gtkwave
  ☆31Updated 3 months ago
• MaxXSoft / Fuxi
  Fuxi (伏羲) is a 32-bit pipelined RISC-V processor written in Chisel3.
  ☆173Updated 4 years ago
• XS-MLVP / picker
  Pick your favorite language to verify your chip.
  ☆51Updated this week
• OSCPU / ysyx-workbench
  ☆151Updated last week
• puckbee / moli
  ☆15Updated last week
• SocialistDalao / UltraMIPS_NSCSCC
  UltraMIPS SoC composed of dual-issue cpu, pipeline Cache and systematic peripheral.
  ☆138Updated last year
• f0rm2l1n / riscv-simulator-guide
  RISC-V模拟器，相关硬件实现`riscv-isa-sim`以及模拟器pk, bbl的指导手册
  ☆53Updated 5 years ago
• tastynoob / aura-core
  "aura" my super-scalar O3 cpu core
  ☆24Updated last year
• NOP-Processor / NOP-Core
  High performance LA32R out-of-order processor core. (NSCSCC 2023 Special Prize)
  ☆81Updated last year