NJU-ProjectN / riscv-tests-am
☆11Updated 8 months ago
Related projects ⓘ
Alternatives and complementary repositories for riscv-tests-am
- Modern co-simulation framework for RISC-V CPUs☆116Updated this week
- A RISC-V core running Debian (and a LoongArch core running Linux).☆20Updated 8 months ago
- ☆56Updated 3 months ago
- Open Source Chip Project by University (OSCPU) - Zhoushan Core☆46Updated 2 years ago
- ☆118Updated this week
- Open-source high-performance non-blocking cache☆67Updated last month
- chipyard in mill :P☆75Updated 11 months ago
- ☆76Updated 2 months ago
- ☆31Updated last month
- The 'missing header' for Chisel☆16Updated 3 weeks ago
- XiangShan Frontend Develop Environment☆45Updated last week
- A Verilator based SoC simulator that allows you to define AXI Slave interface in software.☆43Updated this week
- Run Rocket Chip on VCU128☆27Updated 10 months ago
- 第一届 RISC-V 中国峰会的幻灯片等资料存放☆37Updated last year
- A superscalar RISC-V CPU with out-of-order execution and multi-core support☆54Updated 2 years ago
- 体系结构研讨 + ysyx高阶大纲 (WIP☆114Updated 3 weeks ago
- ☆59Updated 3 months ago
- Fuxi (伏羲) is a 32-bit pipelined RISC-V processor written in Chisel3.☆159Updated 3 years ago
- A simple full system emulator. Currently support RV64IMACSU and MIPS32 and LoongArch32. Capable of booting Linux. Suitable for education …☆107Updated last week
- Run rocket-chip on FPGA☆60Updated 4 months ago
- ☆20Updated 11 months ago
- ☆41Updated 3 months ago
- This is a repo for recording and reporting RISCV platform's test and measurement continuously.☆52Updated 10 months ago
- "aura" my super-scalar O3 cpu core☆24Updated 5 months ago
- RISC-V Vector (RVV) Automatic Tests Generator with full instructions coverage, including self-checking test and signature test (RISC-V Co…☆12Updated 7 months ago
- ☆17Updated last year
- Unofficial guide for ysyx students applying to ShanghaiTech University☆15Updated 4 months ago
- A tool to decode RISC-V and LoongArch and MIPS instructions in gtkwave☆25Updated 7 months ago
- Rewrite XuanTieC910 with chisel3☆11Updated 2 years ago
- a Quad-issue, Out-of-order Superscalar MIPS Processor Implemented in SystemVerilog☆45Updated 10 months ago