Alternatives and similar repositories for gtkwave-filter-process-RISC

Users that are interested in gtkwave-filter-process-RISC are comparing it to the libraries listed below

• tastynoob / aura-core
  "aura" my super-scalar O3 cpu core
  ☆24Updated last year
• ysyx-ta / ysyx-summer-readings
  ☆67Updated last year
• OSCPU / yosys-sta
  ☆86Updated 3 weeks ago
• OpenXiangShan / XiangShan-Design-Doc
  Documentation for XiangShan Design
  ☆36Updated last month
• OSCPU / ysyxSoC
  ☆89Updated 2 months ago
• OSCPU / chisel-playground
  ☆68Updated 9 months ago
• OpenXiangShan / gsim
  ☆63Updated last month
• ftppz / ShanghaiTech-YSYX
  Unofficial guide for ysyx students applying to ShanghaiTech University
  ☆23Updated 9 months ago
• OSCPU-Zhoushan / Zhoushan
  Open Source Chip Project by University (OSCPU) - Zhoushan Core
  ☆53Updated 3 years ago
• OpenXiangShan / Deterload
  Xiangshan deterministic workloads generator
  ☆22Updated 6 months ago
• XS-MLVP / picker
  Pick your favorite language to verify your chip.
  ☆74Updated 3 weeks ago
• puckbee / moli
  ☆34Updated 4 months ago
• cyyself / soc-simulator
  A Verilator based SoC simulator that allows you to define AXI Slave interface in software.
  ☆50Updated 2 months ago
• iFuProcessor / iFuCore
  ☆20Updated last year
• isnthzy / lightsss-chiplab
  本项目已被合并至官方Chiplab中
  ☆13Updated 10 months ago
• OpenXiangShan / difftest
  Modern co-simulation framework for RISC-V CPUs
  ☆159Updated last week
• CmdBlockZQG / rvcore-mini-linux
  Build mini linux for your own RISC-V emulator!
  ☆24Updated last year
• OSCPU / openperf
  ☆11Updated 9 months ago
• Tang-Haojin / YuQuan
  A RISC-V core running Debian (and a LoongArch core running Linux).
  ☆22Updated last week
• loongson-community / open-la500
  Mirror of https://gitee.com/loongson-edu/open-la500.git
  ☆18Updated 11 months ago
• OpenXiangShan / GEM5
  ☆113Updated last week
• arch-simulator-sig / advanced-computer-architecture
  体系结构研讨 + ysyx高阶大纲 (WIP
  ☆188Updated last year
• NOP-Processor / NOP-Core
  High performance LA32R out-of-order processor core. (NSCSCC 2023 Special Prize)
  ☆82Updated 2 years ago
• MAdrid1011 / Zircon
  ☆29Updated 10 months ago
• chipsalliance / rvdecoderdb
  The Scala parser to parse riscv/riscv-opcodes generate
  ☆21Updated 3 months ago
• fluctlight001 / Generic-Cache-Module
  适用于龙芯杯团队赛入门选手的应急cache模块
  ☆31Updated last year
• MrAMS / NagiCore
  顺序单/双发射LA32R处理器 (龙芯杯2024) A LA32R CPU in chisel
  ☆25Updated last year
• MrAMS / verilogModuleAddPrefix
  verilog module add prefix script 可用于ysyx项目添加学号
  ☆13Updated last year
• oscc-web / ysyx-website
  The official website of One Student One Chip project.
  ☆11Updated last month
• Tanggling / BOOMCore
  This is a project created and completed by team BOOM(Beihang OO masters).This is a superscalar processor with a 13-stage out-of-order dua…
  ☆17Updated last year