FurryAcetylCoA / gtkwave-filter-process-RISC
A tool to decode RISC-V and LoongArch and MIPS instructions in gtkwave
☆31Updated last month
Alternatives and similar repositories for gtkwave-filter-process-RISC
Users that are interested in gtkwave-filter-process-RISC are comparing it to the libraries listed below
Sorting:
- "aura" my super-scalar O3 cpu core☆24Updated 11 months ago
- A RISC-V core running Debian (and a LoongArch core running Linux).☆22Updated last year
- Pick your favorite language to verify your chip.☆49Updated last week
- Unofficial guide for ysyx students applying to ShanghaiTech University☆21Updated 2 months ago
- Build mini linux for your own RISC-V emulator!☆19Updated 8 months ago
- ☆66Updated 9 months ago
- ☆63Updated 3 weeks ago
- Open Source Chip Project by University (OSCPU) - Zhoushan Core☆51Updated 2 years ago
- A Verilator based SoC simulator that allows you to define AXI Slave interface in software.☆49Updated 6 months ago
- ☆67Updated 3 months ago
- ☆86Updated last week
- verilog module add prefix script 可用于ysyx项目添加学号☆13Updated last year
- 本项目已被合并至官方Chiplab中☆12Updated 4 months ago
- Documentation for XiangShan Design☆24Updated last week
- Xiangshan deterministic workloads generator☆18Updated 2 months ago
- Basic chisel difftest environment for RTL design (WIP☆18Updated 2 months ago
- The Scala parser to parse riscv/riscv-opcodes generate☆20Updated this week
- ☆27Updated last week
- ☆20Updated last month
- ☆22Updated 2 years ago
- ☆10Updated this week
- ☆11Updated 3 months ago
- ☆36Updated last year
- High performance LA32R out-of-order processor core. (NSCSCC 2023 Special Prize)☆78Updated last year
- 顺序单/双发射LA32R处理器 (龙芯杯2024) A LA32R CPU in chisel☆19Updated 5 months ago
- A framework for building hardware verification platform using software method☆18Updated 2 weeks ago
- ☆35Updated last year
- ☆84Updated this week
- ☆19Updated 9 months ago
- a Quad-issue, Out-of-order Superscalar MIPS Processor Implemented in SystemVerilog☆47Updated last year