Kumonda221-CrO3 / gitlab-runner-vivadoLinks
Vivado in GitLab-Runner for GitLab CI/CD
☆10Updated 3 years ago
Alternatives and similar repositories for gitlab-runner-vivado
Users that are interested in gitlab-runner-vivado are comparing it to the libraries listed below
Sorting:
- 给NEMU移植Linux Kernel!☆22Updated 8 months ago
- Basic chisel difftest environment for RTL design (WIP☆20Updated 10 months ago
- The Scala parser to parse riscv/riscv-opcodes generate☆22Updated last week
- Unofficial guide for ysyx students applying to ShanghaiTech University☆23Updated 11 months ago
- ☆11Updated last month
- Xiangshan deterministic workloads generator☆24Updated 8 months ago
- Build mini linux for your own RISC-V emulator!☆24Updated last year
- ☆65Updated last month
- A Verilator based SoC simulator that allows you to define AXI Slave interface in software.☆51Updated last month
- ☆22Updated 2 years ago
- This is an IDE for YSYX_NPC debuging☆12Updated last year
- 本项目已被合并至官方Chiplab中☆13Updated last year
- Open-source AMBA CHI infrastructures (supporting Issue B, E.b)☆33Updated last week
- A RISC-V core running Debian (and a LoongArch core running Linux).☆22Updated 2 months ago
- ☆30Updated last year
- ☆21Updated 8 months ago
- Documentation for XiangShan Design☆41Updated last week
- Mirror of https://gitee.com/loongson-edu/open-la500.git☆24Updated last year
- A docker image for One Student One Chip's debug exam☆10Updated 2 years ago
- A tool to decode RISC-V and LoongArch and MIPS instructions in gtkwave☆32Updated 9 months ago
- This is a project created and completed by team BOOM(Beihang OO masters).This is a superscalar processor with a 13-stage out-of-order dua…☆17Updated last year
- ☆36Updated 6 months ago
- "aura" my super-scalar O3 cpu core☆25Updated last year
- NSCSCC 2023 The Second Prize. TEAM PUA FROM HDU.☆13Updated 10 months ago
- gem5 FS模式实验手册☆44Updated 2 years ago
- CQU Dual Issue Machine☆38Updated last year
- A fork of Xiangshan for AI☆36Updated last week
- Pick your favorite language to verify your chip.☆77Updated this week
- ☆32Updated 6 months ago
- SystemVerilog implemention of the TAGE branch predictor☆13Updated 4 years ago