Vivado in GitLab-Runner for GitLab CI/CD
☆10Oct 27, 2022Updated 3 years ago
Alternatives and similar repositories for gitlab-runner-vivado
Users that are interested in gitlab-runner-vivado are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- nscscc2024，HPU河南理工大学参赛作品，两仪处理器☆13Aug 24, 2024Updated last year
- Second Prize in NSCSCC 2024. An out-of-order CPU designed by NoAXI team from HDU. 2024年全国大学生计算机系统能力大赛CPU设计赛（龙芯杯）团队赛二等奖作品☆26Sep 14, 2024Updated last year
- 给NEMU移植Linux Kernel!☆23Jun 1, 2025Updated last year
- NSCSCC 2023 The Second Prize. TEAM PUA FROM HDU.☆14Mar 29, 2025Updated last year
- Lower chisel memories to SRAM macros☆13Mar 25, 2024Updated 2 years ago
- GPUs on demand by Runpod - Special Offer Available • AdRun AI, ML, and HPC workloads on powerful cloud GPUs—without limits or wasted spend. Deploy GPUs in under a minute and pay by the second.
- ☆23Apr 16, 2023Updated 3 years ago
- CV32E40X Design-Verification environment☆18Jun 2, 2026Updated last month
- Gemini 30F2 (30F3 variant 00) MIPS Processor for NSCSCC2022☆11Sep 21, 2022Updated 3 years ago
- A RISC-V core running Debian (and a LoongArch core running Linux).☆23Nov 24, 2025Updated 8 months ago
- Build mini linux for your own RISC-V emulator!☆24Sep 11, 2024Updated last year
- Criticality-aware Framework for Modeling Computer Performance☆34Dec 15, 2024Updated last year
- ☆21May 26, 2025Updated last year
- The Scala parser to parse riscv/riscv-opcodes generate☆26Jan 21, 2026Updated 6 months ago
- VSH（SHell for Visualizing vcd file）项目为数字波形文件命令行查看器。☆25Dec 8, 2025Updated 7 months ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- ☆82Oct 29, 2024Updated last year
- Recommended coding standard of Verilog and SystemVerilog.☆37Oct 21, 2021Updated 4 years ago
- RISC-V模拟器，相关硬件实现`riscv-isa-sim`以及模拟器pk, bbl的指导手册☆55Apr 11, 2020Updated 6 years ago
- Fuzzing General-Purpose Hardware Designs with Software Fuzzers☆27Mar 8, 2026Updated 4 months ago
- ☆76Jul 16, 2026Updated last week
- ☆10Mar 19, 2015Updated 11 years ago
- Nix template for the chisel-based industrial designing flows.☆58Jul 21, 2026Updated last week
- A riscv emulator.☆19Feb 5, 2024Updated 2 years ago
- Embedded Development Framework for ECOS SoC Chip.☆17Jul 20, 2026Updated last week
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- Port of MIT's xv6 OS to 32 bit RISC V☆12Feb 12, 2023Updated 3 years ago
- ☆67Aug 5, 2024Updated last year
- Re-coded Xilinx primitives for Verilator use☆54Jun 24, 2025Updated last year
- ☆16Aug 26, 2025Updated 11 months ago
- The 'missing header' for Chisel☆24Feb 5, 2026Updated 5 months ago
- Zircon CPU in 2024☆13Nov 21, 2025Updated 8 months ago
- Learn NVDLA by SOMNIA☆42Dec 13, 2019Updated 6 years ago
- Advanced Architecture Labs with CVA6☆81Jan 16, 2024Updated 2 years ago
- A Customized ASIC framework for Retro Stuff☆26Updated this week
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- ☆35Aug 22, 2023Updated 2 years ago
- ☆32Apr 10, 2026Updated 3 months ago
- ☆15Updated this week
- ☆20Mar 3, 2026Updated 4 months ago
- Xiangshan deterministic workloads generator☆28May 14, 2025Updated last year
- 体系结构研讨 + ysyx高阶大纲 (WIP☆218Oct 14, 2024Updated last year
- Basic chisel difftest environment for RTL design (WIP☆21Mar 8, 2025Updated last year