Alternatives and similar repositories for nscscc2024-liangyi

Users that are interested in nscscc2024-liangyi are comparing it to the libraries listed below

• isnthzy / lightsss-chiplab
  本项目已被合并至官方Chiplab中
  ☆12Updated 6 months ago
• MrAMS / NagiCore
  顺序单/双发射LA32R处理器 (龙芯杯2024) A LA32R CPU in chisel
  ☆23Updated 8 months ago
• fluctlight001 / Generic-Cache-Module
  适用于龙芯杯团队赛入门选手的应急cache模块
  ☆28Updated last year
• Sevenqi7 / NSCSCC-2022
  2022龙芯杯个人赛三等奖作品
  ☆15Updated last year
• OSCPU / openperf
  ☆11Updated 5 months ago
• CmdBlockZQG / rvcore-mini-linux
  Build mini linux for your own RISC-V emulator!
  ☆21Updated 10 months ago
• FurryAcetylCoA / gtkwave-filter-process-RISC
  A tool to decode RISC-V and LoongArch and MIPS instructions in gtkwave
  ☆31Updated 3 months ago
• MaZirui2001 / Zircon
  ☆28Updated 6 months ago
• NoAXI / NoAXI-LoongArch-CPU
  Out-of-order CPU design. Second Prize in NSCSCC 2024. Developed by team NoAXI from Hangzhou Dianzi University.
  ☆19Updated 10 months ago
• loongson-community / open-la500
  Mirror of https://gitee.com/loongson-edu/open-la500.git
  ☆18Updated 7 months ago
• puckbee / moli
  ☆27Updated 2 weeks ago
• YSYX-OpenDoc / riscv-isa-manual
  ☆20Updated 2 months ago
• 1932287243 / NPC_IDE
  This is an IDE for YSYX_NPC debuging
  ☆12Updated 7 months ago
• MrAMS / Nagi
  基于difftest改进的CPU敏捷开发框架（龙芯杯2024）
  ☆24Updated 11 months ago
• OpenXiangShan / gsim
  ☆44Updated this week
• ftppz / ShanghaiTech-YSYX
  Unofficial guide for ysyx students applying to ShanghaiTech University
  ☆22Updated 5 months ago
• Kumonda221-CrO3 / gitlab-runner-vivado
  Vivado in GitLab-Runner for GitLab CI/CD
  ☆10Updated 2 years ago
• iFuProcessor / iFuCore
  ☆19Updated 11 months ago
• secure-v / vsh
  VSH（SHell for Visualizing vcd file）项目为数字波形文件命令行查看器。
  ☆20Updated last month
• Seeker0472 / ysyx-linux
  给NEMU移植Linux Kernel!
  ☆18Updated 2 months ago
• OpenXiangShan / XiangShan-Design-Doc
  Documentation for XiangShan Design
  ☆29Updated 3 weeks ago
• arch-simulator-sig / chisel-env
  Basic chisel difftest environment for RTL design (WIP
  ☆18Updated 4 months ago
• chipsalliance / rvdecoderdb
  The Scala parser to parse riscv/riscv-opcodes generate
  ☆21Updated last month
• tastynoob / aura-core
  "aura" my super-scalar O3 cpu core
  ☆24Updated last year
• ysyx-ta / ysyx-summer-readings
  ☆66Updated last year
• Clo91eaf / PUA-MIPS
  NSCSCC 2023 The Second Prize. TEAM PUA FROM HDU.
  ☆13Updated 4 months ago
• HIT-MaRiver-mips / cpucore-mariver
  ☆35Updated last year
• OpenXiangShan / Deterload
  Xiangshan deterministic workloads generator
  ☆20Updated 2 months ago
• NOP-Processor / NOP-Core
  High performance LA32R out-of-order processor core. (NSCSCC 2023 Special Prize)
  ☆81Updated last year
• cyyself / soc-simulator
  A Verilator based SoC simulator that allows you to define AXI Slave interface in software.
  ☆49Updated 9 months ago