This is an IDE for YSYX_NPC debuging
☆12Dec 10, 2024Updated last year
Alternatives and similar repositories for NPC_IDE
Users that are interested in NPC_IDE are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- ☆11Dec 23, 2025Updated 3 months ago
- Unofficial guide for ysyx students applying to ShanghaiTech University☆23Feb 25, 2025Updated last year
- A riscv emulator.☆19Feb 5, 2024Updated 2 years ago
- ☆29Jun 19, 2025Updated 9 months ago
- 本项目已被合并至官方Chiplab中☆13Jan 13, 2025Updated last year
- ☆21May 26, 2025Updated 9 months ago
- The official website of One Student One Chip project.☆11Feb 5, 2026Updated last month
- Mirror of https://gitee.com/loongson-edu/open-la500.git☆26Jan 2, 2025Updated last year
- A eDSL framework based on Scala and MLIR, focusing on the Hardware design.☆67Updated this week
- ☆67Mar 3, 2026Updated 2 weeks ago
- 顺序单/双发射LA32R处理器 (龙芯杯2024) A LA32R CPU in chisel☆26Jan 25, 2026Updated last month
- ☆12Sep 18, 2024Updated last year
- 无刷电机驱动 程序+电路板 FOC for BLDC motor, code and PCB project☆14Jan 27, 2024Updated 2 years ago
- Basic chisel difftest environment for RTL design (WIP☆20Mar 8, 2025Updated last year
- ☆71Feb 2, 2026Updated last month
- The Scala parser to parse riscv/riscv-opcodes generate☆25Jan 21, 2026Updated 2 months ago
- ☆21Oct 6, 2025Updated 5 months ago
- CPU敏捷开发框架(龙芯杯2024)☆26Sep 6, 2024Updated last year
- RISC-V 64 CPU☆10Oct 4, 2025Updated 5 months ago
- ☆44Dec 5, 2025Updated 3 months ago
- ☆36Jul 22, 2025Updated 8 months ago
- SUSTech CS202 (Computer Organization) Project, with CPU hardware implemented in Chisel(Scala) and software cross-compiled from Rust.☆34Jun 16, 2023Updated 2 years ago
- Generate Linux Perf event tables for Apple Silicon☆17Dec 16, 2025Updated 3 months ago
- nscscc2024,HPU河南理工大学参赛作品,两仪处理器☆11Aug 24, 2024Updated last year
- RISC-V instruction encoding/decoding☆13Mar 22, 2023Updated 3 years ago
- 【2024年新版】国科大 陈云霁 智能计算系统AICS实验代码☆13May 31, 2024Updated last year
- Summary of bugs in Xuantie C9XX core design. include C906/C908/C910/C920☆29Feb 10, 2026Updated last month
- ☆30Jan 23, 2025Updated last year
- Reasoning LLMs optimized for Chisel code generation☆24Jun 19, 2025Updated 9 months ago
- A WebDAV Extension for TinyHTTPD☆18Dec 30, 2024Updated last year
- gem5 FS模式实验手册☆45Mar 8, 2023Updated 3 years ago
- Nix template for the chisel-based industrial designing flows.☆56Apr 23, 2025Updated 11 months ago
- A 32-bit RISC-V SoC on FPGA that supports RT-Thread.☆29Oct 3, 2023Updated 2 years ago
- A sample of using VGA mode 13h on a QEMU RISC-V virt machine.☆16Jun 24, 2025Updated 8 months ago
- An open source SDR SDRAM controller based on the AXI4 bus and verified by FPGA and tapeout. It can support memory particles of different …☆22May 12, 2025Updated 10 months ago
- The 'missing header' for Chisel☆24Feb 5, 2026Updated last month
- Taiwei-3D-Flow☆41Mar 2, 2026Updated 3 weeks ago
- Build mini linux for your own RISC-V emulator!☆24Sep 11, 2024Updated last year
- ☆66Aug 5, 2024Updated last year