oscc-ip / sdram
An open source SDR SDRAM controller based on the AXI4 bus and verified by FPGA and tapeout. It can support memory particles of different manufacturers and models through parameter configuration.
☆16Updated last week
Alternatives and similar repositories for sdram:
Users that are interested in sdram are comparing it to the libraries listed below
- DUTH RISC-V Superscalar Microprocessor☆30Updated 5 months ago
- LCAI-TIHU HW is an AI inference processor which is comprised of RISC-V cpu, nvdla, NoC bus, PCIe module, DDR, SRAM, bootROM, DMA and peri…☆36Updated 2 years ago
- ☆25Updated 4 years ago
- Chisel implementation of Neural Processing Unit for System on the Chip☆21Updated 4 months ago
- Transactional Verilog design and Verilator Testbench for a RISC-V TensorCore Vector co-processor for reproducible linear algebra☆51Updated 3 years ago
- RISCV-VP++ is a extended and improved successor of the RISC-V based Virtual Prototype (VP) RISC-V VP. It is maintained at the Institute f…☆31Updated 3 weeks ago
- SAURIA (Systolic-Array tensor Unit for aRtificial Intelligence Acceleration) is an open-source Convolutional Neural Network accelerator b…☆34Updated 5 months ago
- a hardware design library based on SpinalHDL, especially for stream processing operators on Xilinx FPGAs for Arithmetic, DSP, Communicati…☆59Updated last year
- YSYX RISC-V Project NJU Study Group☆15Updated 2 months ago
- Prototype-network-on-chip (ProNoC) is an EDA tool that facilitates prototyping of custom heterogeneous NoC-based many-core-SoC (MCSoC).☆52Updated last week
- Open-source AMBA CHI infrastructures (supporting Issue B, E.b)☆18Updated this week
- Linux-capable superscalar out-of-order RISC core (with Cache& MMU) and SoC, having been verified on Xilinx Kintex-7 FPGA.☆52Updated 7 months ago
- ☆41Updated 6 years ago
- RiftCore is a 9-stage, single-issue, out-of-order 64-bits RISC-V Core, which supports RV64IMC and 3-level Cache System☆38Updated 2 years ago
- An Open-Source SCAlable Interface for ISA Extensionsfor RISC-V Processors. New Version:☆14Updated last year
- ☆26Updated 5 years ago
- SystemVerilog Functional Coverage for RISC-V ISA☆25Updated 5 months ago
- Advanced Architecture Labs with CVA6☆54Updated last year
- A MCU implementation based PODES-M0O☆18Updated 5 years ago
- General Purpose AXI Direct Memory Access☆49Updated 10 months ago
- Synopsys Verdi applet that presents a view of the source code running on a RISC-V processor with a simulation waveform.☆29Updated 5 years ago
- ☆43Updated 2 years ago
- Cycle-accurate C++ & SystemC simulator for the RISC-V GPGPU Ventus☆24Updated this week
- ☆23Updated 3 weeks ago
- HLS for Networks-on-Chip☆33Updated 4 years ago
- Reconfigurable Binary Engine☆16Updated 4 years ago
- 128KB AXI cache (32-bit in, 256-bit out)☆48Updated 3 years ago
- sram/rram/mram.. compiler☆32Updated last year
- ☆53Updated 4 years ago
- ☆32Updated this week