Alternatives and similar repositories for sdram

Users that are interested in sdram are comparing it to the libraries listed below

• AlessandroCilardo / NaplesPU
  The official NaplesPU hardware code repository
  ☆20Updated 6 years ago
• ljgibbslf / basic_cache_core
  ☆31Updated 5 years ago
• Chainsaw-Team / Chainsaw
  a hardware design library based on SpinalHDL, especially for stream processing operators on Xilinx FPGAs for Arithmetic, DSP, Communicati…
  ☆67Updated last year
• anycore / anycore-riscv-src
  The RTL source for AnyCore RISC-V
  ☆33Updated 3 years ago
• embecosm / ri5cy
  The PULP RI5CY core modified for Verilator modeling and as a GDB server.
  ☆25Updated 6 years ago
• ic-lab-duth / DRIM-S
  DUTH RISC-V Superscalar Microprocessor
  ☆32Updated last year
• cassuto / nano-cpu32k
  Linux-capable superscalar out-of-order RISC core (with Cache& MMU) and SoC, having been verified on Xilinx Kintex-7 FPGA.
  ☆55Updated last year
• sequencer / arithmetic
  ☆33Updated 8 months ago
• ics-jku / riscv-vp-plusplus
  RISCV-VP++ is a extended and improved successor of the RISC-V based Virtual Prototype (VP) RISC-V VP. It is maintained at the Institute f…
  ☆47Updated last month
• freechipsproject / ip-contributions
  For contributions of Chisel IP to the chisel community.
  ☆68Updated last year
• whutddk / RiftCore
  RiftCore is a 9-stage, single-issue, out-of-order 64-bits RISC-V Core, which supports RV64IMC and 3-level Cache System
  ☆44Updated 3 years ago
• RISMicroDevices / CHIron
  Open-source AMBA CHI infrastructures (supporting Issue B, E.b)
  ☆29Updated this week
• pulp-platform / axi_llc
  ☆32Updated last week
• Xilinx / pcie-model
  PCI Express controller model
  ☆70Updated 3 years ago
• pulp-platform / tech_cells_generic
  Technology dependent cells instantiated in the design for generic process (simulation, FPGA)
  ☆70Updated last week
• sifferman / labs-with-cva6
  Advanced Architecture Labs with CVA6
  ☆71Updated last year
• atfox272 / AXI4-Interconnect
  RTL code for AXI4 Interconnect (Verilog). Supports weighted round-robin arbitration, n-channel master, 4Kb splitting, reorder transaction…
  ☆19Updated 8 months ago
• pulp-platform / quadrilatero
  matrix-coprocessor for RISC-V
  ☆25Updated 7 months ago
• stillwater-sc / RISC-V-TensorCore
  Transactional Verilog design and Verilator Testbench for a RISC-V TensorCore Vector co-processor for reproducible linear algebra
  ☆59Updated 3 years ago
• Nuclei-Software / e603_hbird
  RV64GC Linux Capable RISC-V Core
  ☆44Updated last month
• LCAI-TIHU / HW
  LCAI-TIHU HW is an AI inference processor which is comprised of RISC-V cpu, nvdla, NoC bus, PCIe module, DDR, SRAM, bootROM, DMA and peri…
  ☆42Updated 2 years ago
• pulp-platform / redmule
  ☆88Updated last week
• RPTU-EIS / RISCV-Core
  5-stage RISC-V core (RV32IM) with pipelining designed for educational purposes by RPTU Kaiserslautern, Germany
  ☆13Updated last year
• ben-marshall / croyde-riscv
  A barebones 64-bit RISC-V micro-controller class CPU, implementing the I(nteger), M(ul/div), C(ompressed) and K(ryptography) extensions.
  ☆48Updated 3 years ago
• hsa-ees / paranut
  The ParaNut Processor - Highly Parallel and More Than Just a CPU Core
  ☆36Updated 2 years ago
• aignacio / axi_dma
  General Purpose AXI Direct Memory Access
  ☆61Updated last year
• SchaffHub / RISC-Verdi
  Synopsys Verdi applet that presents a view of the source code running on a RISC-V processor with a simulation waveform.
  ☆33Updated 5 years ago
• mpskex / chisel-npu
  Chisel implementation of Neural Processing Unit for System on the Chip
  ☆23Updated 3 months ago
• bsc-loca / sauria
  SAURIA (Systolic-Array tensor Unit for aRtificial Intelligence Acceleration) is an open-source Convolutional Neural Network accelerator b…
  ☆68Updated last week
• cnrv / CNRV-FPU
  Basic floating-point components for RISC-V processors
  ☆67Updated 6 years ago