☆42Dec 5, 2025Updated 2 months ago
Alternatives and similar repositories for espresso
Users that are interested in espresso are comparing it to the libraries listed below
Sorting:
- This is an IDE for YSYX_NPC debuging☆12Dec 10, 2024Updated last year
- 本项目已被合并至官方Chiplab中☆13Jan 13, 2025Updated last year
- RISC-V 64 CPU☆10Oct 4, 2025Updated 4 months ago
- nscscc2024,HPU河南理工大学参赛作品,两仪处理器☆11Aug 24, 2024Updated last year
- CPU敏捷开发框架(龙芯 杯2024)☆25Sep 6, 2024Updated last year
- 顺序单/双发射LA32R处理器 (龙芯杯2024) A LA32R CPU in chisel☆25Jan 25, 2026Updated last month
- 无刷电机驱动 程序+电路板 FOC for BLDC motor, code and PCB project☆14Jan 27, 2024Updated 2 years ago
- ☆15Updated this week
- Taiwei-3D-Flow☆42Updated this week
- Nix template for the chisel-based industrial designing flows.☆52Apr 23, 2025Updated 10 months ago
- ☆67Updated this week
- A repository that implements Tywaves: enabling a type-based waveform debugging for Chisel and Tydi-Chisel. Mapping from Chisel level code…☆58Oct 27, 2024Updated last year
- A riscv emulator.☆19Feb 5, 2024Updated 2 years ago
- The Scala parser to parse riscv/riscv-opcodes generate☆24Jan 21, 2026Updated last month
- A eDSL framework based on Scala and MLIR, focusing on the Hardware design.☆65Updated this week
- Second Prize in NSCSCC 2024. An out-of-order CPU designed by NoAXI team from HDU. 2024年全国大学生计算机系统能力大赛CPU设计赛(龙芯杯)团队赛二等奖作品☆23Sep 14, 2024Updated last year
- Mirror of https://gitee.com/loongson-edu/open-la500.git☆26Jan 2, 2025Updated last year
- ☆36Jul 22, 2025Updated 7 months ago
- Generate Linux Perf event tables for Apple Silicon☆17Dec 16, 2025Updated 2 months ago
- ☆12May 8, 2025Updated 9 months ago
- ☆11Dec 23, 2025Updated 2 months ago
- ☆71Feb 2, 2026Updated last month
- RISC-V instruction encoding/decoding☆13Mar 22, 2023Updated 2 years ago
- Minimal RISC-V Chisel design strictly reflecting the ISA document for verification.☆18Feb 3, 2026Updated last month
- Quickly update a bitstream with new RAM contents☆16Jun 8, 2021Updated 4 years ago
- A framework for ysyx flow☆13Oct 31, 2024Updated last year
- Chisel3 AXI4-{Lite, Full, Stream} Definitions☆15Dec 31, 2018Updated 7 years ago
- ☆13Apr 24, 2024Updated last year
- This repository contains some tools to monitor the UNC_CBO_CACHE_LOOKUP event of the C-Boxes.☆12Oct 11, 2017Updated 8 years ago
- high-performance RTL simulator☆186Jun 19, 2024Updated last year
- The batteries-included testing and formal verification library for Chisel-based RTL designs.☆233Aug 19, 2024Updated last year
- BFM Tester for Chisel HDL☆14Nov 27, 2021Updated 4 years ago
- Enhance CHISEL for Smooth and Comfortable Chip Design☆19Feb 15, 2026Updated 2 weeks ago
- DenseQMC: A bit-slice implementation of the Quine-McCluskey algorithm☆16Dec 30, 2025Updated 2 months ago
- A 32-bit RISC-V SoC on FPGA that supports RT-Thread.☆29Oct 3, 2023Updated 2 years ago
- Advanced Architecture Labs with CVA6☆78Jan 16, 2024Updated 2 years ago
- SUSTech CS202 (Computer Organization) Project, with CPU hardware implemented in Chisel(Scala) and software cross-compiled from Rust.☆34Jun 16, 2023Updated 2 years ago
- Wrapper shells enabling designs generated by rocket-chip to map onto certain FPGA boards☆20Nov 27, 2024Updated last year
- The 'missing header' for Chisel☆23Feb 5, 2026Updated 3 weeks ago