Alternatives and similar repositories for espresso

Users that are interested in espresso are comparing it to the libraries listed below

• freechipsproject / ip-contributions
  For contributions of Chisel IP to the chisel community.
  ☆61Updated 7 months ago
• freechipsproject / chisel-cheatsheet
  Chisel Cheatsheet
  ☆33Updated 2 years ago
• sequencer / arithmetic
  ☆33Updated 2 months ago
• rameloni / tywaves-chisel
  A repository that implements Tywaves: enabling a type-based waveform debugging for Chisel and Tydi-Chisel. Mapping from Chisel level code…
  ☆43Updated 7 months ago
• ucb-bar / chisel-gui
  A prototype GUI for chisel-development
  ☆52Updated 4 years ago
• pulp-platform / culsans
  Tightly-coupled cache coherence unit for CVA6 using the ACE protocol
  ☆32Updated last year
• chipsalliance / tilelink
  ☆30Updated 5 months ago
• YosysHQ-GmbH / SVA-AXI4-FVIP
  YosysHQ SVA AXI Properties
  ☆39Updated 2 years ago
• merledu / caravan
  A caravan equipped with API for creating bus protocols in Chisel with ease.
  ☆14Updated 2 months ago
• rahulk29 / sram22
  A configurable SRAM generator
  ☆50Updated last week
• OpenXiangShan / fudian
  Open source high performance IEEE-754 floating unit
  ☆72Updated last year
• OpenXiangShan / CoupledL2
  Open-source non-blocking L2 cache
  ☆43Updated this week
• pulp-platform / axi_riscv_atomics
  AXI Adapter(s) for RISC-V Atomic Operations
  ☆64Updated 3 weeks ago
• chipsalliance / uvm-verilator
  ☆95Updated last year
• YosysHQ / eqy
  Equivalence checking with Yosys
  ☆43Updated last month
• chipsalliance / playground
  chipyard in mill :P
  ☆78Updated last year
• openhwgroup / cv-hpdcache
  RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores
  ☆78Updated last week
• sifferman / labs-with-cva6
  Advanced Architecture Labs with CVA6
  ☆62Updated last year
• SchaffHub / RISC-Verdi
  Synopsys Verdi applet that presents a view of the source code running on a RISC-V processor with a simulation waveform.
  ☆32Updated 5 years ago
• ccelio / chisel-style-guide
  A Style Guide for the Chisel Hardware Construction Language
  ☆107Updated 3 years ago
• Kuree / hgdb
  Hardware generator debugger
  ☆74Updated last year
• pulp-platform / cheshire-ihp130-o
  ☆44Updated 2 months ago
• grayresearch / CX
  Proposed RISC-V Composable Custom Extensions Specification
  ☆71Updated last year
• anycore / anycore-riscv-src
  The RTL source for AnyCore RISC-V
  ☆32Updated 3 years ago
• ovh / sv2chisel
  (System)Verilog to Chisel translator
  ☆114Updated 3 years ago
• ljwljwljwljw / DiplomaticBackend
  ☆17Updated 3 years ago
• hplp / aes_chisel
  Implementation of the Advanced Encryption Standard in Chisel
  ☆20Updated 3 years ago
• chiselverify / chiselverify
  A dynamic verification library for Chisel.
  ☆151Updated 6 months ago
• sequencer / zaozi
  A eDSL framework based on Scala and MLIR, focusing on the Hardware design.
  ☆36Updated last week
• sld-columbia / hl5
  A 32-bit RISC-V Processor Designed with High-Level Synthesis
  ☆52Updated 5 years ago