Alternatives and similar repositories for ShanghaiTech-YSYX

Users that are interested in ShanghaiTech-YSYX are comparing it to the libraries listed below

• FurryAcetylCoA / gtkwave-filter-process-RISC
  A tool to decode RISC-V and LoongArch and MIPS instructions in gtkwave
  ☆31Updated 5 months ago
• chipsalliance / rvdecoderdb
  The Scala parser to parse riscv/riscv-opcodes generate
  ☆21Updated last month
• arch-simulator-sig / chisel-env
  Basic chisel difftest environment for RTL design (WIP
  ☆18Updated 6 months ago
• Seeker0472 / ysyx-linux
  给NEMU移植Linux Kernel!
  ☆20Updated 4 months ago
• puckbee / moli
  ☆32Updated 2 months ago
• tastynoob / aura-core
  "aura" my super-scalar O3 cpu core
  ☆24Updated last year
• ysyx-ta / ysyx-summer-readings
  ☆67Updated last year
• CmdBlockZQG / rvcore-mini-linux
  Build mini linux for your own RISC-V emulator!
  ☆23Updated last year
• OpenXiangShan / gsim
  ☆55Updated last month
• Tang-Haojin / YuQuan
  A RISC-V core running Debian (and a LoongArch core running Linux).
  ☆22Updated last year
• Kumonda221-CrO3 / gitlab-runner-vivado
  Vivado in GitLab-Runner for GitLab CI/CD
  ☆10Updated 2 years ago
• isnthzy / lightsss-chiplab
  本项目已被合并至官方Chiplab中
  ☆12Updated 8 months ago
• loongson-community / open-la500
  Mirror of https://gitee.com/loongson-edu/open-la500.git
  ☆18Updated 9 months ago
• OSCPU / openperf
  ☆11Updated 7 months ago
• cyyself / soc-simulator
  A Verilator based SoC simulator that allows you to define AXI Slave interface in software.
  ☆49Updated last week
• MaZirui2001 / Zircon
  ☆30Updated 8 months ago
• OpenXiangShan / XiangShan-Design-Doc
  Documentation for XiangShan Design
  ☆32Updated this week
• 1932287243 / NPC_IDE
  This is an IDE for YSYX_NPC debuging
  ☆12Updated 9 months ago
• isnthzy / nscscc2024-liangyi
  nscscc2024，HPU河南理工大学参赛作品，两仪处理器
  ☆11Updated last year
• YSYX-OpenDoc / riscv-isa-manual
  ☆20Updated 4 months ago
• fluctlight001 / Generic-Cache-Module
  适用于龙芯杯团队赛入门选手的应急cache模块
  ☆29Updated last year
• OSCPU / ysyxSoC
  ☆87Updated 2 weeks ago
• OpenXiangShan / Deterload
  Xiangshan deterministic workloads generator
  ☆20Updated 4 months ago
• gmlayer0 / wired
  Linux-capable out-of-order superscaler multicore LoongArch32 (LA32 / LA32R) processor.
  ☆31Updated last year
• MrAMS / verilogModuleAddPrefix
  verilog module add prefix script 可用于ysyx项目添加学号
  ☆13Updated last year
• MrAMS / NagiCore
  顺序单/双发射LA32R处理器 (龙芯杯2024) A LA32R CPU in chisel
  ☆25Updated 10 months ago
• OSCPU / yosys-sta
  ☆83Updated 5 months ago
• Clo91eaf / PUA-MIPS
  NSCSCC 2023 The Second Prize. TEAM PUA FROM HDU.
  ☆13Updated 6 months ago
• OSCPU / chisel-playground
  ☆67Updated 7 months ago
• oscc-web / ysyx-website
  The official website of One Student One Chip project.
  ☆11Updated last month