ftppz / ShanghaiTech-YSYX
Unofficial guide for ysyx students applying to ShanghaiTech University
☆21Updated 2 months ago
Alternatives and similar repositories for ShanghaiTech-YSYX
Users that are interested in ShanghaiTech-YSYX are comparing it to the libraries listed below
Sorting:
- A tool to decode RISC-V and LoongArch and MIPS instructions in gtkwave☆31Updated 3 weeks ago
- The Scala parser to parse riscv/riscv-opcodes generate☆20Updated this week
- Build mini linux for your own RISC-V emulator!☆19Updated 8 months ago
- "aura" my super-scalar O3 cpu core☆24Updated 11 months ago
- Basic chisel difftest environment for RTL design (WIP☆18Updated 2 months ago
- This is an IDE for YSYX_NPC debuging☆12Updated 5 months ago
- A RISC-V core running Debian (and a LoongArch core running Linux).☆22Updated last year
- ☆17Updated last month
- ☆27Updated this week
- A Verilator based SoC simulator that allows you to define AXI Slave interface in software.☆49Updated 6 months ago
- verilog module add prefix script 可用于ysyx项目添加学号☆13Updated last year
- Second Prize in NSCSCC 2024. Developed by team NoAXI from Hangzhou Dianzi University.☆16Updated 7 months ago
- ☆66Updated 9 months ago
- ☆25Updated 3 months ago
- 适用于龙芯杯团队赛入门选手的应急cache模块☆26Updated last year
- nscscc2024，HPU河南理工大学参赛作品，两仪处理器☆10Updated 8 months ago
- NSCSCC 2023 The Second Prize. TEAM PUA FROM HDU.☆12Updated last month
- Documentation for XiangShan Design☆24Updated this week
- ☆11Updated 2 months ago
- 给NEMU移植Linux Kernel!☆16Updated last month
- 顺序单/双发射LA32R处理器 (龙芯杯2024) A LA32R CPU in chisel☆19Updated 5 months ago
- Mirror of https://gitee.com/loongson-edu/open-la500.git☆17Updated 4 months ago
- ☆67Updated 3 months ago
- ☆63Updated 3 weeks ago
- VSH（SHell for Visualizing vcd file）项目为数字波形文件命令行查看器。☆19Updated 3 weeks ago
- 基于difftest改进的CPU敏捷开发框架（龙芯杯2024）☆16Updated 8 months ago
- Vivado in GitLab-Runner for GitLab CI/CD☆9Updated 2 years ago
- 本项目已被合并至官方Chiplab中☆12Updated 4 months ago
- ☆20Updated last month
- ☆86Updated last week