ftppz / ShanghaiTech-YSYXLinks
Unofficial guide for ysyx students applying to ShanghaiTech University
☆22Updated 7 months ago
Alternatives and similar repositories for ShanghaiTech-YSYX
Users that are interested in ShanghaiTech-YSYX are comparing it to the libraries listed below
Sorting:
- ☆32Updated 3 months ago
- The Scala parser to parse riscv/riscv-opcodes generate☆21Updated last month
- A tool to decode RISC-V and LoongArch and MIPS instructions in gtkwave☆31Updated 6 months ago
- Build mini linux for your own RISC-V emulator!☆23Updated last year
- "aura" my super-scalar O3 cpu core☆24Updated last year
- 给NEMU移植Linux Kernel!☆21Updated 4 months ago
- Basic chisel difftest environment for RTL design (WIP☆18Updated 7 months ago
- ☆67Updated last year
- ☆58Updated last week
- ☆11Updated 8 months ago
- A RISC-V core running Debian (and a LoongArch core running Linux).☆22Updated last week
- verilog module add prefix script 可用于ysyx项目添加学号☆13Updated last year
- NSCSCC 2023 The Second Prize. TEAM PUA FROM HDU.☆13Updated 6 months ago
- Second Prize in NSCSCC 2024. Out-of-order CPU design from HDU. 2024年全国大学生计算机系统能力大赛CPU设计赛（龙芯杯）团队赛二等奖作品☆20Updated last year
- ☆20Updated 4 months ago
- Vivado in GitLab-Runner for GitLab CI/CD☆10Updated 2 years ago
- Mirror of https://gitee.com/loongson-edu/open-la500.git☆18Updated 9 months ago
- Documentation for XiangShan Design☆35Updated last week
- 适用于龙芯杯团队赛入门选手的应急cache模块☆30Updated last year
- 本项目已被合并至官方Chiplab中☆12Updated 9 months ago
- ☆30Updated 4 months ago
- ☆87Updated 3 weeks ago
- A Verilator based SoC simulator that allows you to define AXI Slave interface in software.☆49Updated 3 weeks ago
- nscscc2024，HPU河南理工大学参赛作品，两仪处理器☆11Updated last year
- This is an IDE for YSYX_NPC debuging☆12Updated 10 months ago
- ☆29Updated 9 months ago
- 体系结构研讨 + ysyx高阶大纲 (WIP☆181Updated last year
- Xiangshan deterministic workloads generator☆22Updated 5 months ago
- ☆83Updated 6 months ago
- Modern co-simulation framework for RISC-V CPUs☆158Updated last week