ftppz / ShanghaiTech-YSYX
Unofficial guide for ysyx students applying to ShanghaiTech University
☆20Updated 6 months ago
Alternatives and similar repositories for ShanghaiTech-YSYX:
Users that are interested in ShanghaiTech-YSYX are comparing it to the libraries listed below
- A tool to decode RISC-V and LoongArch and MIPS instructions in gtkwave☆27Updated 9 months ago
- "aura" my super-scalar O3 cpu core☆24Updated 8 months ago
- A RISC-V core running Debian (and a LoongArch core running Linux).☆22Updated 11 months ago
- Basic chisel difftest environment for RTL design (WIP☆15Updated 6 months ago
- verilog module add prefix script 可用于ysyx项目添加学号☆13Updated 10 months ago
- The Scala parser to parse riscv/riscv-opcodes generate☆12Updated this week
- ☆61Updated 5 months ago
- NSCSCC 2023 The Second Prize. TEAM PUA FROM HDU.☆10Updated 9 months ago
- 本项目已被合并至官方Chiplab中☆11Updated 2 weeks ago
- ☆11Updated last month
- ☆78Updated last month
- A Verilator based SoC simulator that allows you to define AXI Slave interface in software.☆46Updated 2 months ago
- ☆23Updated last week
- 适用于龙芯杯团队赛入门选手的应急cache模块☆21Updated 10 months ago
- ☆32Updated last year
- CQU Dual Issue Machine☆35Updated 7 months ago
- High performance LA32R out-of-order processor core. (NSCSCC 2023 Special Prize)☆72Updated last year
- ☆57Updated 2 months ago
- ☆31Updated last year
- This is a project created and completed by team BOOM(Beihang OO masters).This is a superscalar processor with a 13-stage out-of-order dua…☆14Updated 4 months ago
- Open Source Chip Project by University (OSCPU) - Zhoushan Core☆47Updated 2 years ago
- ☆49Updated last month
- 体系结构研讨 + ysyx高阶大纲 (WIP☆133Updated 3 months ago
- ☆20Updated last year
- A simple full system emulator. Currently support RV64IMACSU and MIPS32 and LoongArch32. Capable of booting Linux. Suitable for education …☆111Updated 2 months ago
- ☆21Updated last year
- 2022龙芯杯个人赛三等奖作品☆13Updated last year
- Nix template for the chisel-based industrial designing flows.☆34Updated this week