Alternatives and similar repositories for ShanghaiTech-YSYX:

Users that are interested in ShanghaiTech-YSYX are comparing it to the libraries listed below

• tastynoob / aura-core
  "aura" my super-scalar O3 cpu core
  ☆24Updated 9 months ago
• MrAMS / verilogModuleAddPrefix
  verilog module add prefix script 可用于ysyx项目添加学号
  ☆13Updated last year
• chipsalliance / rvdecoderdb
  The Scala parser to parse riscv/riscv-opcodes generate
  ☆15Updated last month
• arch-simulator-sig / chisel-env
  Basic chisel difftest environment for RTL design (WIP
  ☆18Updated last week
• FurryAcetylCoA / gtkwave-filter-process-RISC
  A tool to decode RISC-V and LoongArch and MIPS instructions in gtkwave
  ☆30Updated 11 months ago
• ysyx-ta / ysyx-summer-readings
  ☆62Updated 7 months ago
• Tang-Haojin / YuQuan
  A RISC-V core running Debian (and a LoongArch core running Linux).
  ☆22Updated last year
• fluctlight001 / Generic-Cache-Module
  适用于龙芯杯团队赛入门选手的应急cache模块
  ☆23Updated last year
• OSCPU / openperf
  ☆11Updated last month
• OSCPU / yosys-sta
  ☆58Updated 2 months ago
• cyyself / soc-simulator
  A Verilator based SoC simulator that allows you to define AXI Slave interface in software.
  ☆47Updated 4 months ago
• OSCPU / ysyxSoC
  ☆79Updated last month
• MaZirui2001 / Zircon
  ☆23Updated last month
• isnthzy / lightsss-chiplab
  本项目已被合并至官方Chiplab中
  ☆10Updated 2 months ago
• Clo91eaf / PUA-MIPS
  NSCSCC 2023 The Second Prize. TEAM PUA FROM HDU.
  ☆11Updated 11 months ago
• OSCPU / chisel-playground
  ☆63Updated last month
• OSCPU-Zhoushan / Zhoushan
  Open Source Chip Project by University (OSCPU) - Zhoushan Core
  ☆49Updated 2 years ago
• HIT-MaRiver-mips / cpucore-mariver
  ☆33Updated last year
• Groupsun / riscv-mini-five-stage
  This is my graduation project, a simple processor soft core, which implements RV32I ISA.
  ☆15Updated 5 years ago
• arch-simulator-sig / advanced-computer-architecture
  体系结构研讨 + ysyx高阶大纲 (WIP
  ☆145Updated 5 months ago