A framework for ysyx flow
☆13Oct 31, 2024Updated last year
Alternatives and similar repositories for ysyx-framework
Users that are interested in ysyx-framework are comparing it to the libraries listed below
Sorting:
- 一生一芯RISCV处理器核代码仓库（包括相关工具）☆15Sep 11, 2024Updated last year
- 本项目已被合并至官方Chiplab中☆13Jan 13, 2025Updated last year
- An HBM FPGA based SpMV Accelerator☆17Aug 29, 2024Updated last year
- The Scala parser to parse riscv/riscv-opcodes generate☆24Jan 21, 2026Updated last month
- Basic chisel difftest environment for RTL design (WIP☆20Mar 8, 2025Updated 11 months ago
- Second Prize in NSCSCC 2024. An out-of-order CPU designed by NoAXI team from HDU. 2024年全国大学生计算机系统能力大赛CPU设计赛（龙芯杯）团队赛二等奖作品☆23Sep 14, 2024Updated last year
- ☆36Jul 22, 2025Updated 7 months ago
- "aura" my super-scalar O3 cpu core☆25May 25, 2024Updated last year
- A RISC-V RV32I ISA Single Cycle CPU☆25May 22, 2025Updated 9 months ago
- 一生一芯 ， ysyx ， npc . the repo of the YSYX project . a riscv-64 CPU . writing .☆34Jul 17, 2022Updated 3 years ago
- ☆24Nov 14, 2023Updated 2 years ago
- MathLib DAC 2023 version☆13Sep 11, 2023Updated 2 years ago
- ☆71Feb 2, 2026Updated last month
- RISC-V 64 CPU☆10Oct 4, 2025Updated 5 months ago
- fpga i2c slave verilog hdl rtl☆16Nov 26, 2015Updated 10 years ago
- A tool to parse the obsidian syntax to vuepress☆11Aug 15, 2023Updated 2 years ago
- Synthesis using Synopsys DC and Physical Design flow using Synopsys ICC II, of my RISC-V 5 stage pipelined using 32 nm tech repo☆14Jul 31, 2024Updated last year
- iEDA water-drop training initiative☆13Sep 10, 2024Updated last year
- ☆42Dec 5, 2025Updated 3 months ago
- ☆14Aug 10, 2023Updated 2 years ago
- ☆14Feb 23, 2026Updated last week
- Wavious Wlink☆12Oct 28, 2021Updated 4 years ago
- This is about the implementation of (2,1,4) Convolutional Encoder and Viterbi Decoder using Verilog VHDL.☆13Aug 12, 2020Updated 5 years ago
- 体系结构研讨 + ysyx高阶大纲 (WIP☆200Oct 14, 2024Updated last year
- Nix template for the chisel-based industrial designing flows.☆52Apr 23, 2025Updated 10 months ago
- AxLS: An Open-Source Framework for Netlist Transformation Approximate Logic Synthesis☆13Sep 14, 2025Updated 5 months ago
- ☆13Nov 5, 2024Updated last year
- Visualization tool for designing mesh Network-on-Chips (NoC) and assisting with architecture research☆17Jan 21, 2024Updated 2 years ago
- Tiny Tapeout GDS Action (using OpenLane)☆17Feb 27, 2026Updated last week
- ☆16Jan 18, 2025Updated last year
- A setup for debugging command-line applications on the Windows Subsystem for Linux with VS Code.☆13Apr 1, 2020Updated 5 years ago
- ☆15Updated this week
- ☆10Nov 2, 2023Updated 2 years ago
- 基4booth乘法器设计与验证☆15Apr 28, 2024Updated last year
- ☆15Jan 8, 2022Updated 4 years ago
- Verilog VPI module to dump FST (Fast Signal Trace) databases☆20Sep 19, 2023Updated 2 years ago
- Chisel3 AXI4-{Lite, Full, Stream} Definitions☆15Dec 31, 2018Updated 7 years ago
- This is an IDE for YSYX_NPC debuging☆12Dec 10, 2024Updated last year
- 个人博客 随缘更新 请勿期待QAQ☆12Dec 7, 2025Updated 3 months ago