Alternatives and similar repositories for lightsss-chiplab

Users that are interested in lightsss-chiplab are comparing it to the libraries listed below

• FurryAcetylCoA / gtkwave-filter-process-RISC
  A tool to decode RISC-V and LoongArch and MIPS instructions in gtkwave
  ☆31Updated 2 months ago
• chipsalliance / rvdecoderdb
  The Scala parser to parse riscv/riscv-opcodes generate
  ☆21Updated last week
• 1932287243 / NPC_IDE
  This is an IDE for YSYX_NPC debuging
  ☆12Updated 6 months ago
• Tang-Haojin / YuQuan
  A RISC-V core running Debian (and a LoongArch core running Linux).
  ☆22Updated last year
• Seeker0472 / ysyx-linux
  给NEMU移植Linux Kernel!
  ☆18Updated 3 weeks ago
• arch-simulator-sig / chisel-env
  Basic chisel difftest environment for RTL design (WIP
  ☆18Updated 3 months ago
• OSCPU / openperf
  ☆11Updated 4 months ago
• CmdBlockZQG / rvcore-mini-linux
  Build mini linux for your own RISC-V emulator!
  ☆21Updated 9 months ago
• isnthzy / nscscc2024-liangyi
  nscscc2024，HPU河南理工大学参赛作品，两仪处理器
  ☆10Updated 10 months ago
• puckbee / moli
  ☆15Updated last week
• OpenXiangShan / Deterload
  Xiangshan deterministic workloads generator
  ☆19Updated last month
• Tanggling / BOOMCore
  This is a project created and completed by team BOOM(Beihang OO masters).This is a superscalar processor with a 13-stage out-of-order dua…
  ☆16Updated 8 months ago
• loongson-community / open-la500
  Mirror of https://gitee.com/loongson-edu/open-la500.git
  ☆18Updated 5 months ago
• tastynoob / aura-core
  "aura" my super-scalar O3 cpu core
  ☆24Updated last year
• XS-MLVP / toffee
  A framework for building hardware verification platform using software method
  ☆20Updated 3 weeks ago
• ftppz / ShanghaiTech-YSYX
  Unofficial guide for ysyx students applying to ShanghaiTech University
  ☆21Updated 4 months ago
• NoAXI / NoAXI-LoongArch-CPU
  Second Prize in NSCSCC 2024. Developed by team NoAXI from Hangzhou Dianzi University.
  ☆17Updated 9 months ago
• MrAMS / NagiCore
  顺序单/双发射LA32R处理器 (龙芯杯2024) A LA32R CPU in chisel
  ☆20Updated 7 months ago
• chipsalliance / chisel-interface
  The 'missing header' for Chisel
  ☆20Updated 3 months ago
• Kumonda221-CrO3 / gitlab-runner-vivado
  Vivado in GitLab-Runner for GitLab CI/CD
  ☆10Updated 2 years ago
• MrAMS / Nagi
  基于difftest改进的CPU敏捷开发框架（龙芯杯2024）
  ☆17Updated 9 months ago
• XS-MLVP / picker
  Pick your favorite language to verify your chip.
  ☆50Updated last week
• YSYX-OpenDoc / riscv-isa-manual
  ☆20Updated 3 weeks ago
• observerw / ChiseLLM
  Reasoning LLMs optimized for Chisel code generation
  ☆17Updated this week
• LainChip / LainCore
  Linux-capable in-order superscaler LoongArch32r processor. Silicon-proven.
  ☆42Updated 11 months ago
• lizhirui / DreamCoreV2
  ☆22Updated 2 years ago
• MaZirui2001 / Zircon
  ☆26Updated 5 months ago
• Maxpicca-Li / CDIM
  CQU Dual Issue Machine
  ☆36Updated last year
• OpenXiangShan / XiangShan-Design-Doc
  Documentation for XiangShan Design
  ☆27Updated 3 weeks ago
• cyyself / soc-simulator
  A Verilator based SoC simulator that allows you to define AXI Slave interface in software.
  ☆49Updated 7 months ago