iscas-tis / chisel-formal-verificationLinks
Formal verification tools for Chisel and RISC-V
☆13Updated 11 months ago
Alternatives and similar repositories for chisel-formal-verification
Users that are interested in chisel-formal-verification are comparing it to the libraries listed below
Sorting:
- Minimal RISC-V Chisel design strictly reflecting the ISA document for verification.☆14Updated this week
- Fuzzing General-Purpose Hardware Designs with Software Fuzzers☆17Updated last week
- ☆19Updated 10 months ago
- A collection of tests and benchmarks for the Arc simulation backend of CIRCT☆28Updated 3 months ago
- The 'missing header' for Chisel☆20Updated 2 months ago
- A RISC-V core running Debian (and a LoongArch core running Linux).☆22Updated last year
- Project Repo for the Simulator Independent Coverage Research☆19Updated 2 years ago
- ☆17Updated 3 years ago
- ☆33Updated 2 months ago
- A eDSL framework based on Scala and MLIR, focusing on the Hardware design.☆36Updated this week
- Reasoning LLMs optimized for Chisel code generation☆14Updated last month
- Run Rocket Chip on VCU128☆30Updated 6 months ago
- ☆39Updated last year
- A Modular Open-Source Hardware Fuzzing Framework☆33Updated 3 years ago
- An advanced circuit-based sat solver☆22Updated 3 months ago
- A tutorial for setting up Symbolic Quick Error Detection (SQED) using the model checker, CoSA, on the Ride Core☆12Updated 6 years ago
- Hardware Formal Verification Tool☆52Updated this week
- PyCaliper is Python-based tooling infrastructure that allows the verification and synthesis of specifications (properties) for RTL (e.g.,…☆22Updated 4 months ago
- The Next-gen Language & Compiler Powering Efficient Hardware Design☆26Updated 4 months ago
- Xiangshan deterministic workloads generator☆19Updated 2 weeks ago
- ☆11Updated 3 years ago
- A Formal Verification Framework for Chisel☆18Updated last year
- BTOR2 MLIR project☆25Updated last year
- Open-source AMBA CHI infrastructures (supporting Issue B, E.b)☆19Updated last week
- ☆14Updated 2 months ago
- 本项目已被合并至官方Chiplab中☆12Updated 4 months ago
- ☆14Updated 2 months ago
- A superscalar RISC-V CPU with out-of-order execution and multi-core support☆62Updated 3 years ago
- Open-source non-blocking L2 cache☆43Updated this week
- ☆29Updated this week