iscas-tis / chisel-formal-verificationLinks
Formal verification tools for Chisel and RISC-V
☆13Updated last year
Alternatives and similar repositories for chisel-formal-verification
Users that are interested in chisel-formal-verification are comparing it to the libraries listed below
Sorting:
- Minimal RISC-V Chisel design strictly reflecting the ISA document for verification.☆14Updated 2 months ago
- Fuzzing General-Purpose Hardware Designs with Software Fuzzers☆20Updated last week
- ☆19Updated last year
- ☆17Updated 4 months ago
- The 'missing header' for Chisel☆21Updated 5 months ago
- A collection of tests and benchmarks for the Arc simulation backend of CIRCT☆31Updated this week
- ☆17Updated 3 years ago
- A eDSL framework based on Scala and MLIR, focusing on the Hardware design.☆48Updated last week
- ☆44Updated 7 months ago
- Run Rocket Chip on VCU128☆30Updated 8 months ago
- ☆17Updated 2 months ago
- Wrappers for open source FPU hardware implementations.☆33Updated last year
- ☆18Updated last year
- ☆52Updated last week
- A superscalar RISC-V CPU with out-of-order execution and multi-core support☆63Updated 3 years ago
- ☆33Updated 5 months ago
- The Next-gen Language & Compiler Powering Efficient Hardware Design☆29Updated 7 months ago
- A Modular Open-Source Hardware Fuzzing Framework☆34Updated 3 years ago
- A RISC-V core running Debian (and a LoongArch core running Linux).☆22Updated last year
- CQU Dual Issue Machine☆37Updated last year
- ☆40Updated 2 months ago
- Implementation of Pythia: A Customizable Hardware Prefetching Framework Using Online Reinforcement Learning in Chisel HDL. To know more, …☆17Updated 3 years ago
- Open-source AMBA CHI infrastructures (supporting Issue B, E.b)☆19Updated last week
- Reasoning LLMs optimized for Chisel code generation☆18Updated 2 months ago
- Amazon F1-inspired Xilinx VCU118 hardware design framework☆12Updated 4 years ago
- 给NEMU移植Linux Kernel!☆18Updated 2 months ago
- PyCaliper is Python-based tooling infrastructure that allows the verification and synthesis of specifications (properties) for RTL (e.g.,…☆22Updated 2 months ago
- Implementing the Precise Runahead (HPCA'20) in gem5☆12Updated last year