Alternatives and similar repositories for ORAssistant

Users that are interested in ORAssistant are comparing it to the libraries listed below

• The-OpenROAD-Project / TritonCTS
  Source codes and calibration scripts for clock tree synthesis
  ☆40Updated 5 years ago
• sanggido / OpenDP
  Open Source Detailed Placement engine
  ☆38Updated 5 years ago
• aolofsson / POSH
  ☆44Updated 5 years ago
• RIOSLaboratory / OpenRPDK28
  Open source process design kit for 28nm open process
  ☆59Updated last year
• ALIGN-analoglayout / AnalogDetailedRouter
  Intel's Analog Detailed Router
  ☆39Updated 6 years ago
• RIOSLaboratory / OpenXRAM
  sram/rram/mram.. compiler
  ☆37Updated last year
• JinwooWang / Deep-Learning-For-Analog-Circuit-Sizing
  Combination of Analog Circuit Sizing and DL.
  ☆18Updated 2 years ago
• jinwookjungs / open_design_flow
  OpenDesign Flow Database
  ☆16Updated 6 years ago
• ieee-ceda-datc / datc-rdf-Metrics4ML
  ☆31Updated 3 years ago
• ckchengucsd / SMT-based-STDCELL-Layout-Generator
  SMT-based-STDCELL-Layout-Generator
  ☆18Updated 3 years ago
• The-OpenROAD-Project / OpenRCX
  ☆22Updated 4 years ago
• Xilinx / fpga24_routing_contest
  Runtime-First FPGA Interchange Routing Contest @ FPGA’24
  ☆33Updated last month
• The-OpenROAD-Project / OpeNPDN
  Public repository for Task 6 of OpenROAD project. ML-based PDN synthesis and optimization.
  ☆34Updated 2 years ago
• scale-lab / OpenPhySyn
  EDA physical synthesis optimization kit
  ☆59Updated last year
• jinwookjungs / datc_robust_design_flow
  DATC Robust Design Flow.
  ☆37Updated 5 years ago
• muhammadaldacher / Layout-Design-for-an-8-bit-Microprocessor
  Our project involves the design of an 8-bit microprocessor data-path including 8-byte dual port memory, ALU and barrel shifter using CMOS…
  ☆14Updated 4 years ago
• The-OpenROAD-Project / megaboom
  ☆27Updated last week
• sgherbst / msdsl
  Automatic generation of real number models from analog circuits
  ☆41Updated last year
• NVlabs / INSTA
  ☆77Updated 3 weeks ago
• aolofsson / IDEA
  ☆33Updated 5 years ago
• lnis-uofu / TIGFET-10nm-PDK
  An open source PDK using TIGFET 10nm devices.
  ☆49Updated 2 years ago
• AsFigo / yoYoLint
  SystemVerilog RTL Linter for YoSys
  ☆21Updated 7 months ago
• OpenROAD-Assistant / EDA-Corpus
  Datasets for EDA LLM research
  ☆30Updated 6 months ago
• vsdip / vsdStdCellCharacterizer_sky130
  ☆20Updated 3 years ago
• NVlabs / CircuitOps
  ☆86Updated 3 weeks ago
• sgherbst / sky130-hello-world
  Minimal SKY130 example with self-checking LVS, DRC, and PEX
  ☆23Updated 4 years ago
• bespoke-silicon-group / bsg_sv2v
  A tool that converts SystemVerilog to Verilog. Uses Design Compiler, so it is 100% compatible.
  ☆42Updated 2 years ago
• thesourcerer8 / StdCellLib
  LibreSilicon's Standard Cell Library Generator
  ☆20Updated last year
• Ravenslofty / librecell
  ☆25Updated 4 years ago
• ckchengucsd / SMT-based-STDCELL-Layout-Generator-for-PROBE2.0
  SMT-based Simultaneous Place-&-Route for Standard Cell Synthesis for PROBE 2.0
  ☆18Updated 4 years ago