jinwookjungs / open_design_flow
OpenDesign Flow Database
☆16Updated 6 years ago
Alternatives and similar repositories for open_design_flow:
Users that are interested in open_design_flow are comparing it to the libraries listed below
- Workshop on Open-Source EDA Technology (WOSET)☆49Updated 5 months ago
- Runtime-First FPGA Interchange Routing Contest @ FPGA’24☆33Updated 2 months ago
- DATC RDF☆49Updated 4 years ago
- SMT-based Simultaneous Place-&-Route for Standard Cell Synthesis for PROBE 2.0☆17Updated 4 years ago
- DATC Robust Design Flow.☆37Updated 5 years ago
- fakeram generator for use by researchers who do not have access to commercial ram generators☆35Updated 2 years ago
- ☆34Updated 5 years ago
- Global Router Built for ICCAD Contest 2019☆31Updated 5 years ago
- Collection of digital hardware modules & projects (benchmarks)☆54Updated 5 months ago
- Material for OpenROAD Tutorial at DAC 2020☆47Updated 2 years ago
- Source codes and calibration scripts for clock tree synthesis☆40Updated 5 years ago
- A LEF/DEF Utility.☆28Updated 5 years ago
- ☆43Updated 5 years ago
- ☆25Updated last year
- Intel's Analog Detailed Router☆38Updated 5 years ago
- An Approximate Logic Synthesis Framework based on Boolean Matrix Factorization☆30Updated last year
- EPFL and ISCAS85 combinational benchmark circuits in generic gate verilog☆25Updated 5 years ago
- ☆103Updated 5 years ago
- Open-sourced utilities for initial flow setup, calibration, and other user functions for OpenROAD project☆19Updated 5 years ago
- EDA physical synthesis optimization kit☆52Updated last year
- IDEA project source files☆106Updated 5 months ago
- ☆25Updated 2 years ago
- Project repo for the POSH on-chip network generator☆45Updated last month
- LEF/DEF-based port of Iowa State's open-source FastRoute 4.1☆54Updated 4 years ago
- AMF-Placer 2.0: An open-source timing-driven analytical mixed-size FPGA placer of heterogeneous resources (LUT/FF/LUTRAM/MUX/CARRY/DSP/BR…☆101Updated last year
- GPU-based logic synthesis tool☆81Updated 9 months ago
- An infrastructure for integrated EDA☆38Updated last year
- ILP SAT Detailed Router☆11Updated 5 years ago
- Open Source Detailed Placement engine☆38Updated 5 years ago
- An Open-Source Analytical Placer for Large Scale Heterogeneous FPGAs using Deep-Learning Toolkit☆81Updated 3 months ago