jinwookjungs / open_design_flowLinks
OpenDesign Flow Database
☆16Updated 6 years ago
Alternatives and similar repositories for open_design_flow
Users that are interested in open_design_flow are comparing it to the libraries listed below
Sorting:
- Runtime-First FPGA Interchange Routing Contest @ FPGA’24☆33Updated last month
- DATC Robust Design Flow.☆37Updated 5 years ago
- DATC RDF☆51Updated 4 years ago
- ☆44Updated 5 years ago
- Workshop on Open-Source EDA Technology (WOSET)☆49Updated 7 months ago
- Intel's Analog Detailed Router☆39Updated 5 years ago
- Source codes and calibration scripts for clock tree synthesis☆40Updated 5 years ago
- EDA wiki☆54Updated 2 years ago
- The ANUBIS benchmark suite for Incremental Synthesis☆12Updated 4 years ago
- Global Router Built for ICCAD Contest 2019☆31Updated 5 years ago
- ☆33Updated 5 years ago
- AMC: Asynchronous Memory Compiler☆49Updated 5 years ago
- ☆105Updated 5 years ago
- EDA physical synthesis optimization kit☆59Updated last year
- An Approximate Logic Synthesis Framework based on Boolean Matrix Factorization☆31Updated last year
- Builds, flow and designs for the alpha release☆54Updated 5 years ago
- SMT-based Simultaneous Place-&-Route for Standard Cell Synthesis for PROBE 2.0☆18Updated 4 years ago
- ☆27Updated 7 years ago
- IDEA project source files☆107Updated 8 months ago
- A LEF/DEF Utility.☆31Updated 5 years ago
- Project repo for the POSH on-chip network generator☆48Updated 3 months ago
- CHIPKIT: An agile, reusable open-source framework for rapid test chip development☆41Updated 5 years ago
- A configurable SRAM generator☆53Updated this week
- Open source process design kit for 28nm open process☆59Updated last year
- An open source PDK using TIGFET 10nm devices.☆49Updated 2 years ago
- sram/rram/mram.. compiler☆35Updated last year
- Lake is a framework for generating synthesizable memory modules from a high-level behavioral specification and widely-available memory ma…☆22Updated 3 weeks ago
- A collection of big designs to run post-synthesis simulations with yosys☆49Updated 9 years ago
- Macro placement tool for OpenROAD flow☆23Updated 4 years ago
- A tool that converts SystemVerilog to Verilog. Uses Design Compiler, so it is 100% compatible.☆42Updated 2 years ago