jinwookjungs / open_design_flowLinks
OpenDesign Flow Database
☆16Updated 7 years ago
Alternatives and similar repositories for open_design_flow
Users that are interested in open_design_flow are comparing it to the libraries listed below
Sorting:
- SMT-based Simultaneous Place-&-Route for Standard Cell Synthesis for PROBE 2.0☆18Updated 5 years ago
- Workshop on Open-Source EDA Technology (WOSET)☆48Updated 11 months ago
- ☆44Updated 5 years ago
- DATC Robust Design Flow.☆36Updated 5 years ago
- ☆33Updated 5 years ago
- AMC: Asynchronous Memory Compiler☆51Updated 5 years ago
- ☆107Updated 5 years ago
- Runtime-First FPGA Interchange Routing Contest @ FPGA’24☆34Updated 5 months ago
- DATC RDF☆50Updated 5 years ago
- A LEF/DEF Utility.☆32Updated 6 years ago
- fakeram generator for use by researchers who do not have access to commercial ram generators☆38Updated 2 years ago
- Open-sourced utilities for initial flow setup, calibration, and other user functions for OpenROAD project☆19Updated 6 years ago
- IDEA project source files☆109Updated last month
- A configurable SRAM generator☆57Updated 2 months ago
- ☆20Updated last year
- Intel's Analog Detailed Router☆39Updated 6 years ago
- Source codes and calibration scripts for clock tree synthesis☆40Updated 5 years ago
- Project repo for the POSH on-chip network generator☆52Updated 7 months ago
- Next generation CGRA generator☆116Updated this week
- CHIPKIT: An agile, reusable open-source framework for rapid test chip development☆42Updated 5 years ago
- EDA physical synthesis optimization kit☆62Updated 2 years ago
- An Approximate Logic Synthesis Framework based on Boolean Matrix Factorization☆31Updated 2 years ago
- This is the repository of IPs of the group in USC who is developing Analog Mixed-signal Parameter Search Engine (AMPSE). You can download…☆25Updated 2 years ago
- Open source process design kit for 28nm open process☆67Updated last year
- A tool that converts SystemVerilog to Verilog. Uses Design Compiler, so it is 100% compatible.☆43Updated 2 years ago
- ☆67Updated 2 years ago
- ☆31Updated 3 years ago
- AutoSVA is a tool to automatically generate formal testbenches for unit-level RTL verification. The goal is to, based on annotations made…☆92Updated last year
- An Open-Source Analytical Placer for Large Scale Heterogeneous FPGAs using Deep-Learning Toolkit☆86Updated 6 months ago
- This is a tutorial on standard digital design flow☆79Updated 4 years ago