OSCC-Project / iTrainingLinks
iEDA water-drop training initiative
☆13Updated last year
Alternatives and similar repositories for iTraining
Users that are interested in iTraining are comparing it to the libraries listed below
Sorting:
- This github repository summarizes relevant papers for shift left techniques in electronic design automation (EDA).☆30Updated 4 months ago
- ☆27Updated last year
- MasterRTL: A Pre-Synthesis PPA Estimation Framework for Any RTL Design☆66Updated 8 months ago
- Official implementation of paper "Open3DBench: Open-Source Benchmark for 3D-IC Backend Implementation and PPA Evaluation".☆78Updated 7 months ago
- A framework for building hardware verification platform using software method☆32Updated last month
- A Logic Synthesis tool based on "Mockturtle: EPFL Logic Synthesis Library " and "ABC: System for Sequential Logic Synthesis and Formal Ve…☆39Updated last month
- ☆44Updated last year
- This is a python repo for flattening Verilog☆20Updated last month
- EDA wiki☆136Updated 3 months ago
- ☆52Updated last year
- 关于移植模型至gemmini的文档☆32Updated 3 years ago
- An open-source benchmark for generating design RTL with natural language☆154Updated last year
- The open-sourced version of BOOM-Explorer☆45Updated 2 years ago
- ☆90Updated 2 months ago
- The first version of TritonPart☆31Updated 2 years ago
- Generating Hardware Verification Assertions from Design Specifications via Multi-LLMs☆49Updated last year
- 🕹 OpenPARF: An Open-Source Placement and Routing Framework for Large-Scale Heterogeneous FPGAs with Deep Learning Toolkit☆169Updated 9 months ago
- Verification environment for the OpenHW Group's CORE-V High Performance Data Cache controller.☆20Updated last month
- ☆65Updated last month
- ☆95Updated 7 months ago
- A framework for ysyx flow☆13Updated last year
- Collection of digital hardware modules & projects (benchmarks)☆80Updated 2 months ago
- Official implementation of DATE'25 paper "Timing-Driven Global Placement by Efficient Critical Path Extraction".☆61Updated 7 months ago
- Pick your favorite language to verify your chip.☆77Updated last week
- FAN (fan-out-oriented) ATPG (Automatic Test Pattern Generation) and Fault Simulation command line tool☆107Updated 7 months ago
- ☆92Updated 4 months ago
- An integrated CGRA design framework☆91Updated 10 months ago
- Generative Benchmark for LLM-Aided Hardware Design☆26Updated 8 months ago
- GPU-based logic synthesis tool☆97Updated 2 months ago
- A hardware synthesis framework with multi-level paradigm☆44Updated last year