chipfoundry / openlane2Links
The next generation of OpenLane, rewritten from scratch with a modular architecture
☆329Updated last month
Alternatives and similar repositories for openlane2
Users that are interested in openlane2 are comparing it to the libraries listed below
Sorting:
- Fully Open Source FASOC generators built on top of open-source EDA tools☆306Updated 3 months ago
- Caravel is a standard SoC template with on chip resources to control and read/write operations from a user-dedicated space.☆376Updated 11 months ago
- PDK installer for open-source EDA tools and toolchains. Distributed with setups for the SkyWater 130nm and Global Foundries 180nm open p…☆386Updated 3 weeks ago
- https://caravel-user-project.readthedocs.io☆225Updated 11 months ago
- Qflow full end-to-end digital synthesis flow for ASIC designs☆223Updated last year
- Fabric generator and CAD tools.☆214Updated last week
- 130nm BiCMOS Open Source PDK, dedicated for Analog, Mixed Signal and RF Design. Documentation is here:☆664Updated last week
- ASIC implementation flow infrastructure, successor to OpenLane☆256Updated last week
- ☆375Updated 2 years ago
- IEEE Solid-State Circuits Society (SSCS) Open-Source Ecosystem (OSE)☆200Updated 3 weeks ago
- ☆122Updated 2 years ago
- Standard Cell Library based Memory Compiler using FF/Latch cells☆163Updated 2 months ago
- Course material for a basic hands-on analog circuit design course with IC emphasis☆177Updated this week
- This repo is a fork of the master OpenLANE repo for us with projects submitted on Efabless Open MPW or chipIgnite shuttles:: OpenLANE is …☆160Updated last year
- SystemVerilog synthesis tool☆225Updated 10 months ago
- A schematic editor for VLSI/Asic/Analog custom designs, netlist backends for VHDL, Spice and Verilog. The tool is focused on hierarchy an…☆436Updated this week
- CORE-V Family of RISC-V Cores☆318Updated 11 months ago
- OpenROAD's scripts implementing an RTL-to-GDS Flow. Documentation at https://openroad-flow-scripts.readthedocs.io/en/latest/☆554Updated this week
- Universal Hardware Data Model. A complete modeling of the IEEE SystemVerilog Object Model with VPI Interface, Elaborator, Serialization, …☆245Updated 4 months ago
- OpenROAD users should look at this repository first for instructions on getting started☆101Updated 4 years ago
- ☆187Updated 4 years ago
- A PULP SoC for education, easy to understand and extend with a full flow for a physical design.☆200Updated this week
- PDK for GlobalFoundries' 180nm MCU bulk process technology (GF180MCU).☆456Updated 2 years ago
- Hammer: Highly Agile Masks Made Effortlessly from RTL☆308Updated 3 months ago
- EE 628: Analysis and Design of Integrated Circuits (University of Hawaiʻi at Mānoa)☆174Updated 5 months ago
- ☆173Updated 2 years ago
- Magic VLSI Layout Tool☆605Updated this week
- Physical Design Flow from RTL to GDS using Opensource tools.☆118Updated 5 years ago
- A minimal Linux-capable 64-bit RISC-V SoC built around CVA6☆316Updated last week
- Test suite designed to check compliance with the SystemVerilog standard.☆356Updated this week