Alternatives and similar repositories for Differentiable-Global-Router

Users that are interested in Differentiable-Global-Router are comparing it to the libraries listed below

• lamda-bbo / Efficient-TDP
  Official implementation of DATE'25 paper "Timing-Driven Global Placement by Efficient Critical Path Extraction".
  ☆44Updated 3 weeks ago
• ABKGroup / BlobPlacement
  ☆13Updated 11 months ago
• cuhk-eda / CULS
  GPU-based logic synthesis tool
  ☆81Updated 10 months ago
• cuhk-eda / GCS-Timer
  ☆20Updated 7 months ago
• ABKGroup / TritonRoute-WXL
  ☆30Updated 4 years ago
• ABKGroup / TritonPart
  The first version of TritonPart
  ☆26Updated last year
• cuhk-eda / Xplace
  Xplace 3.0: An Extremely Fast, Extensible and Deterministic Placement Framework with Detailed-Routability and Timing Optimization
  ☆122Updated last week
• asyncvlsi / SPRoute
  A parallel global router using the Galois framework
  ☆29Updated last year
• zshi0616 / python-deepgate
  ☆22Updated 11 months ago
• ieee-ceda-datc / datc-rdf-Metrics4ML
  ☆31Updated 3 years ago
• The-OpenROAD-Project-Attic / FastRoute
  LEF/DEF-based port of Iowa State's open-source FastRoute 4.1
  ☆55Updated 4 years ago
• cuhk-eda / cu-gr-2
  ☆44Updated last year
• liangrj2014 / ISPD25_contest
  ☆10Updated last month
• panhomyoung / phyLS
  A Logic Synthesis tool based on "Mockturtle: EPFL Logic Synthesis Library " and "ABC: System for Sequential Logic Synthesis and Formal Ve…
  ☆26Updated last month
• jinwookjungs / datc_robust_design_flow
  DATC Robust Design Flow.
  ☆37Updated 5 years ago
• lamda-bbo / Open3DBench
  Official implementation of paper "Open3DBench: Open-Source Benchmark for 3D-IC Backend Implementation and PPA Evaluation".
  ☆25Updated this week
• cuhk-eda / cu-gr
  CUGR, VLSI Global Routing Tool Developed by CUHK
  ☆136Updated 2 years ago
• TILOS-AI-Institute / HypergraphPartitioning
  Hypergraph Partitioning: benchmarks, evaluators, best known solutions and codes
  ☆68Updated this week
• cuhk-eda / dr-cu
  Dr. CU, VLSI Detailed Routing Tool Developed by CUHK
  ☆134Updated 2 years ago
• ispras / hdl-benchmarks
  Collection of digital hardware modules & projects (benchmarks)
  ☆59Updated 3 weeks ago
• zslwyuan / AutoCellLibX
  AutoCellLibX: Automated Standard Cell Library Extension Based on Pattern Mining
  ☆15Updated 2 years ago
• zshi0616 / DeepGate2
  ☆28Updated last year
• santoshsmalagi / Benchmarks
  A collection of ISCAS,ITC,TAU and other Benchmark Circuits for EDA tool evaluation.
  ☆48Updated 4 months ago
• ieee-ceda-datc / RDF-2019
  DATC RDF
  ☆50Updated 4 years ago
• cuhk-eda / ripple
  Pin-Accessible Legalization for Mixed-Cell-Height Circuits
  ☆29Updated 3 years ago
• jkim971201 / SkyPlace
  ☆17Updated 8 months ago
• IntelLabs / FloorSet
  ☆72Updated 5 months ago
• liangrj2014 / ISPD24_contest
  ☆20Updated 4 months ago
• daeyeon22 / artificial_netlist_generator
  Artificial Netlist Generator
  ☆39Updated last year
• geziangfinn / easyPlace
  Reimplementation of the VLSI placement algorithm: ePlace and ePlace-MS
  ☆39Updated 7 months ago