Alternatives and similar repositories for Differentiable-Global-Router

Users that are interested in Differentiable-Global-Router are comparing it to the libraries listed below

• ABKGroup / BlobPlacement
  ☆13Updated 11 months ago
• lamda-bbo / Efficient-TDP
  Official implementation of DATE'25 paper "Timing-Driven Global Placement by Efficient Critical Path Extraction".
  ☆45Updated last week
• cuhk-eda / CULS
  GPU-based logic synthesis tool
  ☆81Updated this week
• ABKGroup / TritonRoute-WXL
  ☆30Updated 4 years ago
• bu-icsg / TAP-2.5D
  ☆33Updated 4 years ago
• ABKGroup / TritonPart
  The first version of TritonPart
  ☆27Updated last year
• cuhk-eda / GCS-Timer
  ☆22Updated 2 weeks ago
• cuhk-eda / cu-gr-2
  ☆44Updated last year
• zshi0616 / python-deepgate
  ☆22Updated last year
• zslwyuan / AutoCellLibX
  AutoCellLibX: Automated Standard Cell Library Extension Based on Pattern Mining
  ☆15Updated 2 years ago
• ispras / hdl-benchmarks
  Collection of digital hardware modules & projects (benchmarks)
  ☆59Updated last month
• cuhk-eda / Xplace
  Xplace 3.0: An Extremely Fast, Extensible and Deterministic Placement Framework with Detailed-Routability and Timing Optimization
  ☆127Updated last week
• cuhk-eda / cu-gr
  CUGR, VLSI Global Routing Tool Developed by CUHK
  ☆136Updated 2 years ago
• ieee-ceda-datc / datc-rdf-Metrics4ML
  ☆31Updated 3 years ago
• hkust-zhiyao / MasterRTL
  MasterRTL: A Pre-Synthesis PPA Estimation Framework for Any RTL Design
  ☆50Updated 3 weeks ago
• cuhk-eda / ripple
  Pin-Accessible Legalization for Mixed-Cell-Height Circuits
  ☆29Updated 3 years ago
• liangrj2014 / ISPD24_contest
  ☆20Updated 5 months ago
• liangrj2014 / ISPD25_contest
  ☆10Updated 2 months ago
• CODA-Team / AnalogGym
  ☆48Updated 3 weeks ago
• The-OpenROAD-Project-Attic / FastRoute
  LEF/DEF-based port of Iowa State's open-source FastRoute 4.1
  ☆56Updated 4 years ago
• panhomyoung / phyLS
  A Logic Synthesis tool based on "Mockturtle: EPFL Logic Synthesis Library " and "ABC: System for Sequential Logic Synthesis and Formal Ve…
  ☆28Updated this week
• Ravenslofty / librecell
  ☆24Updated 4 years ago
• asyncvlsi / SPRoute
  A parallel global router using the Galois framework
  ☆29Updated last year
• lamda-bbo / Open3DBench
  Official implementation of paper "Open3DBench: Open-Source Benchmark for 3D-IC Backend Implementation and PPA Evaluation".
  ☆30Updated 2 weeks ago
• TILOS-AI-Institute / HypergraphPartitioning
  Hypergraph Partitioning: benchmarks, evaluators, best known solutions and codes
  ☆69Updated 3 weeks ago
• TimingPredict / Dataset
  Timing prediction dataset download and instructions.
  ☆15Updated 2 years ago
• daeyeon22 / artificial_netlist_generator
  Artificial Netlist Generator
  ☆39Updated last year
• zshi0616 / DeepGate2
  ☆28Updated last year
• Yu-Maryland / Verilog-to-PyG
  ☆25Updated last year
• IntelLabs / FloorSet
  ☆72Updated last week