FAN (fan-out-oriented) ATPG (Automatic Test Pattern Generation) and Fault Simulation command line tool
☆111Jul 2, 2025Updated 10 months ago
Alternatives and similar repositories for FAN_ATPG
Users that are interested in FAN_ATPG are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Atalanta is a modified ATPG (Automatic Test Pattern Generation) tool and fault simulator, orginally from VirginiaTech University.☆91May 7, 2024Updated 2 years ago
- An automatic test pattern generation (ATPG) and fault simulation system.☆12Sep 9, 2019Updated 6 years ago
- SAT-based ATPG using TG-Pro model☆19Jun 5, 2018Updated 7 years ago
- An ATPG tool using PODEM algorithm in C++ that generates a test to detect any given list of Single-Stuck-at Faults☆11Oct 29, 2017Updated 8 years ago
- Problems and Results of IWLS 2023 Programming Contest☆17Apr 12, 2025Updated last year
- Simple, predictable pricing with DigitalOcean hosting • AdAlways know what you'll pay with monthly caps and flat pricing. Enterprise-grade infrastructure trusted by 600k+ customers.
- A complete open-source design-for-testing (DFT) Solution☆189Aug 30, 2025Updated 8 months ago
- GPU-based logic synthesis tool☆102Mar 31, 2026Updated last month
- ELVE : ELVE Logic Visualization Engine☆11Jul 2, 2017Updated 8 years ago
- Logic circuit analysis and optimization☆48Feb 2, 2026Updated 3 months ago
- Optimized Circuit Generation for Secure Multiparty Computation☆12Nov 25, 2019Updated 6 years ago
- QuteRTL: A RTL Front-End Towards Intelligent Synthesis and Verification☆16Nov 8, 2016Updated 9 years ago
- Gamora: Graph Learning based Symbolic Reasoning for Large-Scale Boolean Networks (DAC'23)☆58Jan 8, 2025Updated last year
- Hypergraph Partitioning: benchmarks, evaluators, best known solutions and codes☆87Jan 15, 2026Updated 3 months ago
- An advanced header-only exact synthesis library☆31Nov 24, 2022Updated 3 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- Automatic Test Pattern Generation using PODEM algorithm☆15May 12, 2014Updated 11 years ago
- Logic Synthesis System from UC Berkeley (Unofficial Distribution)☆15Jun 4, 2019Updated 6 years ago
- ☆9Jul 20, 2023Updated 2 years ago
- A collection of ISCAS,ITC,TAU and other Benchmark Circuits for EDA tool evaluation.☆72Apr 30, 2026Updated last week
- ☆19Dec 21, 2020Updated 5 years ago
- A standalone structural (gate-level) verilog parser☆41Mar 20, 2026Updated last month
- A logic synthesis tool☆88Apr 20, 2026Updated 3 weeks ago
- IDEA project source files☆112Apr 15, 2026Updated 3 weeks ago
- Semi-Tenser Product based SAT and AllSAT solver, where it can solve CNF and circuit input.☆17Aug 2, 2023Updated 2 years ago
- End-to-end encrypted email - Proton Mail • AdSpecial offer: 40% Off Yearly / 80% Off First Month. All Proton services are open source and independently audited for security.
- C++ implementation of FRAIGs. Won the 1st place in 2018 Cadence-sponsored contest in NTU DSnP.☆10Oct 21, 2020Updated 5 years ago
- C++ header-only exact synthesis library☆18Jan 18, 2023Updated 3 years ago
- A Logic Synthesis tool based on "Mockturtle: EPFL Logic Synthesis Library " and "ABC: System for Sequential Logic Synthesis and Formal Ve…☆42Apr 10, 2026Updated last month
- Arche is a Greek word with primary senses "beginning". The repository defines a framework for technology mapping of emerging technologies…☆11May 15, 2020Updated 5 years ago
- Open Source Detailed Placement engine☆13Feb 19, 2020Updated 6 years ago
- OpenABC-D is a large-scale labeled dataset generated by synthesizing open source hardware IPs. This dataset can be used for various graph…☆148Jul 23, 2025Updated 9 months ago
- MapTune: Advancing ASIC Technology Mapping via Reinforcement Learning Guided Library Tuning Mingju Liu, Daniel Robinson, Yingjie Li, Cunx…☆28Apr 9, 2025Updated last year
- MasterRTL: A Pre-Synthesis PPA Estimation Framework for Any RTL Design☆71May 29, 2025Updated 11 months ago
- C++ Implementation of reduced order binary decision diagram data structure☆13Nov 11, 2015Updated 10 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- KaHyPar (Karlsruhe Hypergraph Partitioning) is a multilevel hypergraph partitioning framework providing direct k-way and recursive bisect…☆518Mar 7, 2026Updated 2 months ago
- SIMPLER MAGIC: Synthesis and In-memory MaPping of Logic Execution in a single Row for Memristor Aided loGIC☆13Dec 5, 2019Updated 6 years ago
- Problems and Results of IWLS 2022 Programming Contest☆23Apr 12, 2025Updated last year
- ☆16Feb 9, 2022Updated 4 years ago
- EPFL logic synthesis benchmarks☆248Updated this week
- ☆23Mar 13, 2023Updated 3 years ago
- ☆31Apr 23, 2024Updated 2 years ago