NTU-LaDS-II / FAN_ATPG
FAN (fan-out-oriented) ATPG (Automatic Test Pattern Generation) and Fault Simulation command line tool
☆86Updated last year
Alternatives and similar repositories for FAN_ATPG:
Users that are interested in FAN_ATPG are comparing it to the libraries listed below
- ASIC Design Kit for FreePDK45 + Nangate for use with mflowgen☆171Updated 5 years ago
- EPFL and ISCAS85 combinational benchmark circuits in generic gate verilog☆26Updated 5 years ago
- MasterRTL: A Pre-Synthesis PPA Estimation Framework for Any RTL Design☆46Updated 7 months ago
- An Open-Source Analytical Placer for Large Scale Heterogeneous FPGAs using Deep-Learning Toolkit☆81Updated this week
- ☆155Updated last month
- 🕹 OpenPARF: An Open-Source Placement and Routing Framework for Large-Scale Heterogeneous FPGAs with Deep Learning Toolkit☆140Updated last week
- Atalanta is a modified ATPG (Automatic Test Pattern Generation) tool and fault simulator, orginally from VirginiaTech University.☆78Updated 11 months ago
- A collection of ISCAS,ITC,TAU and other Benchmark Circuits for EDA tool evaluation.☆45Updated 3 months ago
- This is a tutorial on standard digital design flow☆76Updated 3 years ago
- IDEA project source files☆106Updated 5 months ago
- reference block design for the ASAP7nm library in Cadence Innovus☆41Updated 10 months ago
- INT8 & FP16 multiplier accumulator (MAC) design with UVM verification completed.☆99Updated 4 years ago
- Introductory course into static timing analysis (STA).☆90Updated last week
- Collection of digital hardware modules & projects (benchmarks)☆55Updated this week
- AMF-Placer 2.0: An open-source timing-driven analytical mixed-size FPGA placer of heterogeneous resources (LUT/FF/LUTRAM/MUX/CARRY/DSP/BR…☆102Updated last year
- RTL Network-on-Chip Router Design in SystemVerilog by Andrea Galimberti, Filippo Testa and Alberto Zeni☆126Updated 7 years ago
- ☆67Updated this week
- An integrated CGRA design framework☆88Updated last month
- This repository has a list of collaterals needed for ICC2 workshop. It has a modified version of raven_soc which was taped-out by Efables…☆31Updated 4 years ago
- ☆43Updated last year
- ☆22Updated 10 months ago
- ☆23Updated 4 years ago
- Re-host of ISCAS89 sequential benchmark circuits in higher level verilog (without "DFF")☆14Updated 3 years ago
- Physical Design Flow from RTL to GDS using Opensource tools.☆99Updated 4 years ago
- A verilog implementation for Network-on-Chip☆73Updated 7 years ago
- Incremental Timing-Driven Placement, problem C of ICCAD contest 2015☆13Updated 7 years ago
- An AXI4 crossbar implementation in SystemVerilog☆145Updated this week
- AutoSVA is a tool to automatically generate formal testbenches for unit-level RTL verification. The goal is to, based on annotations made…☆81Updated last year
- ☆42Updated 7 months ago
- Design of 1024x32 SRAM (32Kbits) using OpenRAM and SKY130 PDKs with operating voltage of 1.8V and access time < 2.5ns☆66Updated 4 years ago