nputikhin / sat_atpgLinks
SAT-based ATPG using TG-Pro model
☆16Updated 7 years ago
Alternatives and similar repositories for sat_atpg
Users that are interested in sat_atpg are comparing it to the libraries listed below
Sorting:
- EPFL and ISCAS85 combinational benchmark circuits in generic gate verilog☆27Updated 5 years ago
- Combinational ATPG generator based on D-Algorithm☆16Updated 4 years ago
- This is a python repo for flattening Verilog☆18Updated last month
- Collection of digital hardware modules & projects (benchmarks)☆59Updated last month
- Re-host of ISCAS89 sequential benchmark circuits in higher level verilog (without "DFF")☆14Updated 3 years ago
- DATC Robust Design Flow.☆37Updated 5 years ago
- An automatic test pattern generation (ATPG) and fault simulation system.☆11Updated 5 years ago
- MasterRTL: A Pre-Synthesis PPA Estimation Framework for Any RTL Design☆50Updated 3 weeks ago
- ☆25Updated last year
- EDA physical synthesis optimization kit☆58Updated last year
- Annotating Slack Directly on Your Verilog: Fine-Grained RTL Timing Evaluation for Early Optimization☆29Updated 3 weeks ago
- ☆44Updated last year
- AutoSVA is a tool to automatically generate formal testbenches for unit-level RTL verification. The goal is to, based on annotations made…☆83Updated last year
- GPU-based logic synthesis tool☆81Updated this week
- FAN (fan-out-oriented) ATPG (Automatic Test Pattern Generation) and Fault Simulation command line tool☆92Updated last year
- ☆22Updated last year
- OpenDesign Flow Database☆16Updated 6 years ago
- DATC RDF☆50Updated 4 years ago
- A Logic Synthesis tool based on "Mockturtle: EPFL Logic Synthesis Library " and "ABC: System for Sequential Logic Synthesis and Formal Ve…☆28Updated this week
- A custom C++ routine to identify logic gates in the layout extracted netlist (SPICE) of digital circuits and generate gate-level Verilog …☆30Updated 10 months ago
- LEF/DEF-based port of Iowa State's open-source FastRoute 4.1☆56Updated 4 years ago
- ☆24Updated 4 years ago
- A collection of ISCAS,ITC,TAU and other Benchmark Circuits for EDA tool evaluation.☆50Updated 5 months ago
- ☆16Updated 4 years ago
- Incremental Timing-Driven Placement, problem C of ICCAD contest 2015☆13Updated 7 years ago
- Courseworks of CS6165 VLSI Physical Design Automation, NTHU.☆46Updated 4 years ago
- Open Source Detailed Placement engine☆38Updated 5 years ago
- Logic optimization and technology mapping tool.☆18Updated last year
- AMF-Placer 2.0: An open-source timing-driven analytical mixed-size FPGA placer of heterogeneous resources (LUT/FF/LUTRAM/MUX/CARRY/DSP/BR…☆105Updated last year
- Atalanta is a modified ATPG (Automatic Test Pattern Generation) tool and fault simulator, orginally from VirginiaTech University.☆81Updated last year