SAT-based ATPG using TG-Pro model
☆19Jun 5, 2018Updated 7 years ago
Alternatives and similar repositories for sat_atpg
Users that are interested in sat_atpg are comparing it to the libraries listed below
Sorting:
- An automatic test pattern generation (ATPG) and fault simulation system.☆12Sep 9, 2019Updated 6 years ago
- Combinational ATPG generator based on D-Algorithm☆16Nov 25, 2020Updated 5 years ago
- Random Generator of Btor2 Files☆10Sep 2, 2023Updated 2 years ago
- Arithmetic multiplier benchmarks☆12Nov 13, 2017Updated 8 years ago
- ☆13Feb 6, 2021Updated 5 years ago
- ☆13Jan 20, 2023Updated 3 years ago
- ☆14Sep 14, 2020Updated 5 years ago
- Atalanta is a modified ATPG (Automatic Test Pattern Generation) tool and fault simulator, orginally from VirginiaTech University.☆88May 7, 2024Updated last year
- ☆15May 24, 2023Updated 2 years ago
- ☆15Nov 9, 2022Updated 3 years ago
- Java library for parsing and manipulating graph representations of gate-level Verilog netlists☆15Jan 9, 2017Updated 9 years ago
- ☆20Jun 12, 2024Updated last year
- This is a repo to store circuit design datasets☆19Jan 17, 2024Updated 2 years ago
- libCircuit is a C++ Library for EDA software development☆18Sep 27, 2018Updated 7 years ago
- Bᴛᴏʀ2MLIR: A Format and Toolchain for Hardware Verification☆20Sep 4, 2025Updated 6 months ago
- ☆17Nov 19, 2023Updated 2 years ago
- ☆19Jan 2, 2026Updated 2 months ago
- Logic Synthesis System from UC Berkeley (Unofficial Distribution)☆15Jun 4, 2019Updated 6 years ago
- ☆49Apr 10, 2024Updated last year
- ☆19Jul 12, 2024Updated last year
- Methodology that leverages FPV to automatically discover covert channels in hardware that is time-shared between processes. AutoCC operat…☆22Oct 25, 2024Updated last year
- Logic optimization and technology mapping tool.☆20Oct 12, 2023Updated 2 years ago
- BTOR2 MLIR project☆26Jan 17, 2024Updated 2 years ago
- FAN (fan-out-oriented) ATPG (Automatic Test Pattern Generation) and Fault Simulation command line tool☆108Jul 2, 2025Updated 8 months ago
- Library Exchange Format (LEF) and Design Exchange Format (DEF)☆24Aug 13, 2020Updated 5 years ago
- Fast Symbolic Repair of Hardware Design Code☆33Jan 20, 2025Updated last year
- AMulet 2. - A better AIG Multiplier Examination Tool☆26Dec 23, 2025Updated 2 months ago
- ILA Model Database☆24Sep 27, 2020Updated 5 years ago
- PyTorch implementation of NeuroSAT☆28May 21, 2023Updated 2 years ago
- A custom C++ routine to identify logic gates in the layout extracted netlist (SPICE) of digital circuits and generate gate-level Verilog …☆33Aug 21, 2024Updated last year
- ☆41Oct 10, 2025Updated 4 months ago
- 21st century electronic design automation tools, written in Rust.☆36Feb 23, 2026Updated last week
- Automated Repair of Verilog Hardware Descriptions☆35Jan 16, 2025Updated last year
- 在這系列文中我會從最基礎的編輯器推薦、語言選擇、環境建置、框架介紹、自動化部署、資料庫架設、到一個簡單的部落格貼文 API 範例實作以及單元測試和簡單的雲端平台服務,希望能幫助到各位實戰的經驗。☆10Apr 5, 2020Updated 5 years ago
- A tool for checking the contract satisfaction for hardware designs☆12Nov 4, 2025Updated 4 months ago
- ☆15Apr 19, 2017Updated 8 years ago
- This is an Implementation of CAN BUS protocol with STM32☆17Feb 14, 2021Updated 5 years ago
- ☆14Jan 11, 2021Updated 5 years ago
- Generating Hardware Verification Assertions from Design Specifications via Multi-LLMs☆50Oct 28, 2024Updated last year