Alternatives and similar repositories for sat_atpg

Users that are interested in sat_atpg are comparing it to the libraries listed below

• jpsety / verilog_benchmark_circuits
  EPFL and ISCAS85 combinational benchmark circuits in generic gate verilog
  ☆28Updated 5 years ago
• HKUSTGZ-MICS-LYU / FlattenRTL
  This is a python repo for flattening Verilog
  ☆20Updated 5 months ago
• ispras / hdl-benchmarks
  Collection of digital hardware modules & projects (benchmarks)
  ☆65Updated 2 weeks ago
• amahzoon / genmul
  ☆18Updated 4 years ago
• PrincetonUniversity / AutoSVA
  AutoSVA is a tool to automatically generate formal testbenches for unit-level RTL verification. The goal is to, based on annotations made…
  ☆91Updated last year
• cuhk-eda / CULS
  GPU-based logic synthesis tool
  ☆93Updated 3 months ago
• NTU-LaDS-II / FAN_ATPG
  FAN (fan-out-oriented) ATPG (Automatic Test Pattern Generation) and Fault Simulation command line tool
  ☆97Updated 4 months ago
• Yu-Maryland / Verilog-to-PyG
  ☆27Updated last year
• HKUST-GZ-VLSI / Design-Dataset
  This is a repo to store circuit design datasets
  ☆19Updated last year
• scale-lab / OpenPhySyn
  EDA physical synthesis optimization kit
  ☆62Updated last year
• Entropy-xcy / sns
  ☆20Updated 3 years ago
• ehw-fit / ariths-gen
  Generator of arithmetic circuits (multipliers, adders) and approximate circuits
  ☆35Updated 2 months ago
• gpt4rtl / AutoSVA2
  ☆17Updated last year
• shahsaumya00 / D-Algorithm-Combinational
  Combinational ATPG generator based on D-Algorithm
  ☆16Updated 4 years ago
• hkust-zhiyao / AssertLLM
  Generating Hardware Verification Assertions from Design Specifications via Multi-LLMs
  ☆39Updated last year
• OSCC-Project / iMap
  Logic optimization and technology mapping tool.
  ☆19Updated 2 years ago
• sanggido / OpenDP
  Open Source Detailed Placement engine
  ☆39Updated 5 years ago
• lnis-uofu / LSOracle
  IDEA project source files
  ☆108Updated 3 weeks ago
• hkust-zhiyao / MasterRTL
  MasterRTL: A Pre-Synthesis PPA Estimation Framework for Any RTL Design
  ☆58Updated 5 months ago
• nbulsi / also
  A logic synthesis tool
  ☆82Updated 2 months ago
• jinwookjungs / datc_robust_design_flow
  DATC Robust Design Flow.
  ☆36Updated 5 years ago
• rachelselinar / DREAMPlaceFPGA
  An Open-Source Analytical Placer for Large Scale Heterogeneous FPGAs using Deep-Learning Toolkit
  ☆85Updated 6 months ago
• ieee-ceda-datc / RDF-2019
  DATC RDF
  ☆50Updated 5 years ago
• zslwyuan / AMF-Placer
  AMF-Placer 2.0: An open-source timing-driven analytical mixed-size FPGA placer of heterogeneous resources (LUT/FF/LUTRAM/MUX/CARRY/DSP/BR…
  ☆106Updated last year
• panhomyoung / phyLS
  A Logic Synthesis tool based on "Mockturtle: EPFL Logic Synthesis Library " and "ABC: System for Sequential Logic Synthesis and Formal Ve…
  ☆34Updated 3 months ago
• hsluoyz / Atalanta
  Atalanta is a modified ATPG (Automatic Test Pattern Generation) tool and fault simulator, orginally from VirginiaTech University.
  ☆82Updated last year
• Xilinx / fpga24_routing_contest
  Runtime-First FPGA Interchange Routing Contest @ FPGA’24
  ☆33Updated 5 months ago
• Ghonimo / Formal-Verification-With-VC-Formal--Tutorials-and-Examples
  This repository is dedicated to providing a comprehensive guide and practical examples for using VC Formal for formal verification. Our g…
  ☆38Updated last year
• cure-lab / DeepGate2
  ☆16Updated 2 years ago
• ekiwi / rtl-repair
  Fast Symbolic Repair of Hardware Design Code
  ☆28Updated 9 months ago