DfX-NYUAD / GNNUnlock

Related projects ⓘ

Alternatives and complementary repositories for GNNUnlock

• daeyeon22 / artificial_netlist_generator
  Artificial Netlist Generator
  ☆32Updated 7 months ago
• ispras / hdl-benchmarks
  Collection of digital hardware modules & projects (benchmarks)
  ☆31Updated last week
• Yu-Maryland / Gamora
  Gamora: Graph Learning based Symbolic Reasoning for Large-Scale Boolean Networks (DAC'23)
  ☆47Updated this week
• cad-polito-it / I99T
  ITC'99 benchmarks developed in the CAD Group at Politecnico di Torino
  ☆47Updated last year
• santoshsmalagi / Benchmarks
  A collection of ISCAS,ITC,TAU and other Benchmark Circuits for EDA tool evaluation.
  ☆33Updated last month
• DfX-NYUAD / GNN-RE
  GNN-RE datasets for circuit recognition
  ☆38Updated last year
• jpsety / verilog_benchmark_circuits
  EPFL and ISCAS85 combinational benchmark circuits in generic gate verilog
  ☆23Updated 4 years ago
• IntelLabs / FloorSet
  ☆50Updated 2 weeks ago
• hkust-zhiyao / APPLE
  A circuit-element level explainer to explain machine learning model's prediction on chip layouts.
  ☆17Updated last year
• DfX-NYUAD / GNN4IC
  Must-read papers on Graph Neural Networks (GNNs) for Integrated Circuits (ICs) design, security and reliability. This collection of paper…
  ☆39Updated last year
• cure-lab / DeepGate
  This is an official implementation for "DeepGate: Learning Neural Representations of Logic Gates".
  ☆19Updated last year
• Yu-Maryland / Verilog-to-PyG
  ☆20Updated 6 months ago
• wjrforcyber / ABCPaperCheck
  Research paper based on or related to ABC.
  ☆15Updated this week
• ieee-ceda-datc / RDF-2019
  DATC RDF
  ☆48Updated 4 years ago
• jinwookjungs / datc_robust_design_flow
  DATC Robust Design Flow.
  ☆37Updated 4 years ago
• hkust-zhiyao / RTL-Timer
  Annotating Slack Directly on Your Verilog: Fine-Grained RTL Timing Evaluation for Early Optimization
  ☆17Updated 4 months ago
• zshi0616 / python-deepgate
  ☆21Updated 4 months ago
• cuhk-eda / CULS
  GPU-based logic synthesis tool
  ☆67Updated 3 months ago
• hkust-zhiyao / MasterRTL
  MasterRTL: A Pre-Synthesis PPA Estimation Framework for Any RTL Design
  ☆35Updated last month
• panhomyoung / phyLS
  A Logic Synthesis tool based on "Mockturtle: EPFL Logic Synthesis Library " and "ABC: System for Sequential Logic Synthesis and Formal Ve…
  ☆18Updated last month
• Centre-for-Hardware-Security / asap7_reference_design
  reference block design for the ASAP7nm library in Cadence Innovus
  ☆32Updated 4 months ago
• rachelselinar / DREAMPlaceFPGA
  An Open-Source Analytical Placer for Large Scale Heterogeneous FPGAs using Deep-Learning Toolkit
  ☆75Updated 2 weeks ago
• tsung-wei-huang / ece5960-physical-design
  ☆36Updated last year
• ABKGroup / PROBE3.0
  ☆36Updated 7 months ago
• alanminko / iwls2022-ls-contest
  Problems and Results of IWLS 2022 Programming Contest
  ☆16Updated 2 years ago
• bluesceada / iscas89_hl_verilog
  Re-host of ISCAS89 sequential benchmark circuits in higher level verilog (without "DFF")
  ☆13Updated 2 years ago
• zshi0616 / DeepGate2
  ☆27Updated 11 months ago
• NYU-MLDA / OpenABC
  OpenABC-D is a large-scale labeled dataset generated by synthesizing open source hardware IPs. This dataset can be used for various graph…
  ☆114Updated last month
• ieee-ceda-datc / datc-rdf-Metrics4ML
  ☆28Updated 2 years ago
• bu-icsg / TAP-2.5D
  ☆23Updated 3 years ago