Alternatives and similar repositories for quaigh

Users that are interested in quaigh are comparing it to the libraries listed below

• ucb-substrate / substrate2
  21st century electronic design automation tools, written in Rust.
  ☆31Updated this week
• ekiwi / wellen
  wellen: waveform datastructures in Rust. Fast VCD, FST and GHW parsing for waveform viewers.
  ☆89Updated last month
• mikeurbach / egg-netlist-synthesizer
  Using e-graphs to synthesize netlists from boolean logic.
  ☆14Updated 2 years ago
• broccolimicro / loom
  design and verification of asynchronous circuits
  ☆40Updated this week
• hudson-trading / slang-server
  A SystemVerilog language server based on the Slang parser and library.
  ☆36Updated this week
• Kuree / hgdb
  Hardware generator debugger
  ☆76Updated last year
• djg / verilated-rs
  Verilator Porcelain
  ☆48Updated last year
• AUCOHL / Lighter
  An automatic clock gating utility
  ☆50Updated 5 months ago
• ThePerfectComputer / FastWaveBackend
  A Rust VCD parser intended to be the backend of a Waveform Viewer(built using egui) that supports dynamically loaded rust plugins.
  ☆48Updated 9 months ago
• Kuree / kratos
  Debuggable hardware generator
  ☆70Updated 2 years ago
• lachlansneff / ligeia
  A replacement for gtkwave, written in Rust with high-performance and larger-than-memory traces in mind.
  ☆19Updated 3 years ago
• YosysHQ / eqy
  Equivalence checking with Yosys
  ☆46Updated last week
• YosysHQ / mcy
  Mutation Cover with Yosys (MCY)
  ☆87Updated 3 weeks ago
• fabianschuiki / moore
  A hardware compiler based on LLHD and CIRCT
  ☆262Updated 3 months ago
• ymherklotz / verismith
  Verilog Fuzzer to test the major simulators and sythesisers by generating random, valid Verilog.
  ☆115Updated 4 months ago
• antmicro / sv-bugpoint
  ☆30Updated last week
• prjunnamed / prjunnamed
  End-to-end synthesis and P&R toolchain
  ☆89Updated last week
• chipsalliance / fpga-interchange-schema
  ☆56Updated 3 years ago
• rdaly525 / coreir
  ☆103Updated 3 years ago
• lip6 / coriolis
  Coriolis VLSI EDA Tool (LIP6)
  ☆72Updated 2 weeks ago
• pulp-platform / morty
  A SystemVerilog source file pickler.
  ☆60Updated 11 months ago
• CTSRD-CHERI / TestRIG
  Testing processors with Random Instruction Generation
  ☆46Updated last month
• microsoft / Elastic-Silicon-Interconnect
  ESI is an FPGA connectivity system. It uses typed, latency-insensitive on-chip connections between ESI-enabled modules. It also bridges o…
  ☆34Updated 5 years ago
• vegaluisjose / vast
  Verilog AST
  ☆21Updated last year
• benbr8 / rstb
  Rust Test Bench - write HDL tests in Rust.
  ☆23Updated 2 years ago
• kevinmehall / rust-vcd
  Read and write VCD (Value Change Dump) files in Rust
  ☆44Updated last year
• cristian-mattarei / CoSA
  CoreIR Symbolic Analyzer
  ☆74Updated 4 years ago
• ethanuppal / marlin
  🦀 No-nonsense hardware testing/simulation in Rust 🛠️ | Verilog, Spade, Veryl
  ☆65Updated last month
• IntelLabs / pycaliper
  PyCaliper is Python-based tooling infrastructure that allows the verification and synthesis of specifications (properties) for RTL (e.g.,…
  ☆22Updated 3 months ago
• povik / yosys-slang
  SystemVerilog frontend for Yosys
  ☆165Updated this week