Coloquinte / quaighLinks
Logic circuit analysis and optimization
☆45Updated 4 months ago
Alternatives and similar repositories for quaigh
Users that are interested in quaigh are comparing it to the libraries listed below
Sorting:
- 21st century electronic design automation tools, written in Rust.☆33Updated last week
- design and verification of asynchronous circuits☆42Updated 3 weeks ago
- wellen: waveform datastructures in Rust. Fast VCD, FST and GHW parsing for waveform viewers.☆104Updated 2 weeks ago
- Hardware generator debugger☆77Updated last year
- Equivalence checking with Yosys☆54Updated last month
- Using e-graphs to synthesize netlists from boolean logic.☆14Updated 2 years ago
- A Rust VCD parser intended to be the backend of a Waveform Viewer(built using egui) that supports dynamically loaded rust plugins.☆49Updated last year
- An automatic clock gating utility☆51Updated 8 months ago
- A SystemVerilog language server based on the Slang library.☆100Updated this week
- Verilog Fuzzer to test the major simulators and sythesisers by generating random, valid Verilog.☆116Updated 7 months ago
- Debuggable hardware generator☆70Updated 2 years ago
- Verilator Porcelain☆49Updated 2 years ago
- ☆34Updated last week
- Mutation Cover with Yosys (MCY)☆89Updated last month
- A SystemVerilog source file pickler.☆60Updated last year
- Testing processors with Random Instruction Generation☆50Updated last month
- A collection of tests and benchmarks for the Arc simulation backend of CIRCT☆33Updated this week
- Rust Test Bench - write HDL tests in Rust.☆24Updated 3 years ago
- ☆59Updated 3 years ago
- Fast PnR toolchain for CGRA☆18Updated last year
- CoreIR Symbolic Analyzer☆74Updated 5 years ago
- ☆104Updated 3 years ago
- SystemVerilog frontend for Yosys☆186Updated this week
- Read and write VCD (Value Change Dump) files in Rust☆44Updated last year
- A place to share libraries and utilities that don't belong in the core bsc repo☆37Updated 2 months ago
- ESI is an FPGA connectivity system. It uses typed, latency-insensitive on-chip connections between ESI-enabled modules. It also bridges o…☆35Updated 5 years ago
- YosysHQ SVA AXI Properties☆43Updated 2 years ago
- Verilog AST☆21Updated 2 years ago
- Structural Netlist API (and more) for EDA post synthesis flow development☆129Updated this week
- A replacement for gtkwave, written in Rust with high-performance and larger-than-memory traces in mind.☆19Updated 3 years ago