Alternatives and similar repositories for atpg-PODEM

Users that are interested in atpg-PODEM are comparing it to the libraries listed below

• sanketkkeni / PODEM-Algorithm-implementation
  An ATPG tool using PODEM algorithm in C++ that generates a test to detect any given list of Single-Stuck-at Faults
  ☆11Updated 7 years ago
• mongrelgem / Verilog-Adders
  Implementing Different Adder Structures in Verilog
  ☆67Updated 5 years ago
• avashist003 / SystemVerilog_Design_Verification
  Various RTL design blocks along with verification testbenches with SVAs. Designed using SystemVerilog
  ☆25Updated 2 years ago
• sheldonucr / ee260_lab
  EE 260 Winter 2017: Advanced VLSI Design
  ☆62Updated 8 years ago
• akilm / Physical-Design
  Physical Design Flow from RTL to GDS using Opensource tools.
  ☆101Updated 4 years ago
• shariethernet / Physical-Design-with-OpenLANE-using-SKY130-PDK
  This project is done in the course of "Advanced Physical Design using OpenLANE/Sky130" workshop by VLSI System Design Corporation. In thi…
  ☆44Updated 3 years ago
• openformal / sva_basics
  This repository is compilation of basics of System Verilog Assertions in context of formal verification
  ☆20Updated 6 years ago
• aebeljs / VeRLPy
  VeRLPy is an open-source python library developed to improve the digital hardware verification process by using Reinforcement Learning (R…
  ☆25Updated 2 years ago
• aignacio / axi_dma
  General Purpose AXI Direct Memory Access
  ☆49Updated last year
• A-T-Kristensen / simple-alu-uvm
  This is full tutorial of UVM (Universal Verification Methodology) for a simple ALU unit
  ☆24Updated 6 years ago
• harshithsn / Universal-Shift-Register
  This project give overview of RTL to GDSII of universal shift register using OpenLane and Skywater130 PDK. OpenLane is an automated open-…
  ☆11Updated 2 years ago
• VerificationExcellence / SystemVerilogAssertions
  Examples and reference for System Verilog Assertions
  ☆83Updated 8 years ago
• TL-X-org / TL-V_Projects
  An overview of TL-Verilog resources and projects
  ☆78Updated last month
• brabect1 / sta_basics_course
  Introductory course into static timing analysis (STA).
  ☆94Updated 3 weeks ago
• hanysalah / Design-Pattern-in-SV
  This repo is created to include illustrative examples on object oriented design pattern in SV
  ☆56Updated 2 years ago
• olofk / fifo
  Generic FIFO implementation with optional FWFT
  ☆57Updated 4 years ago
• JonathanJing / Asynchronous-FIFO
  Asynchronous fifo in verilog
  ☆33Updated 9 years ago
• mitshine / UVM-and-System-Verilog-Manual
  UVM and System Verilog Manuals
  ☆42Updated 6 years ago
• amamory-verification / uvm-basics
  my UVM training projects
  ☆33Updated 6 years ago
• ShonTaware / OpenSource_Physical_Design
  This repository contains all the contents studied and created during the Advanced Physical Design Workshop using OpenLANE and SKY130 PDK
  ☆38Updated 3 years ago
• varunnagpaal / Digital-Hardware-Modelling
  Digital Hardware Modelling using VHDL, Verilog, SystemVerilog, SystemC, HLS(C++, OpenCL)
  ☆65Updated 3 months ago
• yvnr4you / AMBA_AXI3
  System Verilog and Emulation. Written all the five channels.
  ☆34Updated 8 years ago
• yathAg / openroad_vsd_7nmContest
  ☆15Updated 2 years ago
• hibagus / 64pointFFTProcessor
  Synthesizeable VHDL and Verilog implementation of 64-point FFT/IFFT Processor with Q4.12 Fixed Point Data Format.
  ☆30Updated 4 years ago
• intel / aib-phy-hardware
  ☆66Updated 2 years ago
• PrincetonUniversity / AutoSVA
  AutoSVA is a tool to automatically generate formal testbenches for unit-level RTL verification. The goal is to, based on annotations made…
  ☆83Updated last year
• tharunchitipolu / Dadda-Multiplier-using-CSA
  Dadda multiplier(8*8, 16*16, 32*32) in Verilog HDL.
  ☆34Updated 11 months ago
• pontazaricardo / Verilog_Calculator_Matrix_Multiplication
  This is a simple project that shows how to multiply two 3x3 matrixes in Verilog.
  ☆49Updated 7 years ago
• Practical-UVM-Step-By-Step / Practical-UVM-IEEE-Edition
  This is the repository for the IEEE version of the book
  ☆58Updated 4 years ago
• pulp-platform / common_verification
  SystemVerilog modules and classes commonly used for verification
  ☆48Updated 4 months ago