Alternatives and similar repositories for atpg

Users that are interested in atpg are comparing it to the libraries listed below

• shahsaumya00 / D-Algorithm-Combinational
  Combinational ATPG generator based on D-Algorithm
  ☆16Updated 4 years ago
• hsluoyz / Atalanta
  Atalanta is a modified ATPG (Automatic Test Pattern Generation) tool and fault simulator, orginally from VirginiaTech University.
  ☆81Updated last year
• nputikhin / sat_atpg
  SAT-based ATPG using TG-Pro model
  ☆16Updated 7 years ago
• NTU-LaDS-II / FAN_ATPG
  FAN (fan-out-oriented) ATPG (Automatic Test Pattern Generation) and Fault Simulation command line tool
  ☆90Updated last year
• twweeb / VLSI-Physical-Design-Automation
  Courseworks of CS6165 VLSI Physical Design Automation, NTHU.
  ☆44Updated 4 years ago
• yellekelyk / PyVerilog
  Python-based Verilog Parser (currently Netlist only)
  ☆54Updated 8 years ago
• cibyr / lefdef
  Library Exchange Format (LEF) and Design Exchange Format (DEF)
  ☆19Updated 4 years ago
• brabect1 / sta_basics_course
  Introductory course into static timing analysis (STA).
  ☆94Updated last month
• bojackchen / digital-flow
  This is a tutorial on standard digital design flow
  ☆78Updated 4 years ago
• akilm / Physical-Design
  Physical Design Flow from RTL to GDS using Opensource tools.
  ☆102Updated 4 years ago
• liyanqing1987 / libertyParser
  liberty parser (For parsing IC timing lib file)
  ☆58Updated last year
• sanggido / OpenDP
  Open Source Detailed Placement engine
  ☆38Updated 5 years ago
• ben-marshall / verilog-vcd-parser
  A parser for Value Change Dump (VCD) files as specified in the IEEE System Verilog 1800-2012 standard.
  ☆95Updated 3 years ago
• ahmedshahein / DSP-RTL-Lib
  RTL Verilog library for various DSP modules
  ☆88Updated 3 years ago
• jasonlin316 / RISC-V-CPU
  A RISC-V 5-stage pipelined CPU that supports vector instructions. Tape-out with U18 technology.
  ☆130Updated 5 years ago
• Daikon-Sun / Physical-Design-for-Nanometer-ICs
  Assignments of Physical Design for Nanometer ICs (Spring 2017, Prof. Yao-Wen Chang)
  ☆41Updated 6 years ago
• freecores / dma_ahb
  AHB DMA 32 / 64 bits
  ☆55Updated 10 years ago
• ieee-ceda-datc / RDF-2019
  DATC RDF
  ☆50Updated 4 years ago
• OpenTimer / Parser-Verilog
  A Standalone Structural Verilog Parser
  ☆92Updated 3 years ago
• Centre-for-Hardware-Security / asap7_reference_design
  reference block design for the ASAP7nm library in Cadence Innovus
  ☆44Updated 11 months ago
• luckyrantanplan / nthu-route
  VLSI EDA Global Router
  ☆73Updated 7 years ago
• vaughnbetz / COFFE
  ☆42Updated 8 months ago
• UNSAMDCI / PDK_ONC5
  Educational Design Kit for Synopsys Tools with a set of Characterized Standard Cell Library
  ☆33Updated 3 years ago
• sanketkkeni / PODEM-Algorithm-implementation
  An ATPG tool using PODEM algorithm in C++ that generates a test to detect any given list of Single-Stuck-at Faults
  ☆11Updated 7 years ago
• mongrelgem / Verilog-Adders
  Implementing Different Adder Structures in Verilog
  ☆70Updated 5 years ago
• Muriukidavid / systemc-examples
  A repository for SystemC Learning examples
  ☆68Updated 2 years ago
• Ravenslofty / librecell
  ☆24Updated 4 years ago
• jimwang99 / parser-for-chip-design
  A set of Python based parsers for multiple file format used in IC chip design, including Verilog, SPICE, lib (Synopsys Liberty).
  ☆31Updated 9 years ago
• pkuzjx / eda-collection
  ☆105Updated 5 years ago
• emwzq / example_uvm
  UVM实战随书源码
  ☆51Updated 6 years ago