Alternatives and similar repositories for Atalanta:

Users that are interested in Atalanta are comparing it to the libraries listed below

• vaughnbetz / COFFE
  ☆40Updated 5 months ago
• OpenTimer / Parser-Verilog
  A Standalone Structural Verilog Parser
  ☆86Updated 2 years ago
• NTU-LaDS-II / FAN_ATPG
  FAN (fan-out-oriented) ATPG (Automatic Test Pattern Generation) and Fault Simulation command line tool
  ☆82Updated last year
• brabect1 / sta_basics_course
  Introductory course into static timing analysis (STA).
  ☆83Updated 3 months ago
• parallaxsw / OpenSTA
  ☆56Updated last week
• ben-marshall / verilog-vcd-parser
  A parser for Value Change Dump (VCD) files as specified in the IEEE System Verilog 1800-2012 standard.
  ☆91Updated 2 years ago
• mflowgen / freepdk-45nm
  ASIC Design Kit for FreePDK45 + Nangate for use with mflowgen
  ☆161Updated 4 years ago
• bojackchen / digital-flow
  This is a tutorial on standard digital design flow
  ☆73Updated 3 years ago
• jpsety / verilog_benchmark_circuits
  EPFL and ISCAS85 combinational benchmark circuits in generic gate verilog
  ☆25Updated 5 years ago
• spider-tronix / Standard-Cell-Characterization
  Open Source tool to build liberty files and for Characterizing Standard Cells.
  ☆24Updated 4 years ago
• bespoke-silicon-group / bsg_fakeram
  fakeram generator for use by researchers who do not have access to commercial ram generators
  ☆35Updated 2 years ago
• The-OpenROAD-Project / asap7
  ☆124Updated 7 months ago
• PrincetonUniversity / AutoSVA
  AutoSVA is a tool to automatically generate formal testbenches for unit-level RTL verification. The goal is to, based on annotations made…
  ☆75Updated 10 months ago
• ispras / hdl-benchmarks
  Collection of digital hardware modules & projects (benchmarks)
  ☆41Updated 3 months ago
• veripool / verilog-perl
  Verilog parser, preprocessor, and related tools for the Verilog-Perl package
  ☆126Updated last year
• AUCOHL / Fault
  A complete open-source design-for-testing (DFT) Solution
  ☆145Updated 3 months ago
• santoshsmalagi / Benchmarks
  A collection of ISCAS,ITC,TAU and other Benchmark Circuits for EDA tool evaluation.
  ☆43Updated last month
• yellekelyk / PyVerilog
  Python-based Verilog Parser (currently Netlist only)
  ☆53Updated 7 years ago
• accellera / uvm
  ☆45Updated 8 years ago
• lnis-uofu / LSOracle
  IDEA project source files
  ☆102Updated 3 months ago
• pkuzjx / eda-collection
  ☆102Updated 5 years ago
• ncsu-eda / FreePDK3
  ☆133Updated 3 years ago
• rahulk29 / sram22_sky130_macros
  SKY130 SRAM macros generated by SRAM 22
  ☆11Updated 2 weeks ago
• ABKGroup / PROBE3.0
  ☆37Updated 10 months ago
• zslwyuan / AMF-Placer
  AMF-Placer 2.0: An open-source timing-driven analytical mixed-size FPGA placer of heterogeneous resources (LUT/FF/LUTRAM/MUX/CARRY/DSP/BR…
  ☆98Updated 11 months ago
• esynr3z / axi_vip_demo
  Xilinx AXI VIP example of use
  ☆33Updated 3 years ago
• UNSAMDCI / PDK_ONC5
  Educational Design Kit for Synopsys Tools with a set of Characterized Standard Cell Library
  ☆31Updated 3 years ago
• pku-dasys / pillars
  An integrated CGRA design framework
  ☆85Updated 3 months ago
• The-OpenROAD-Project-Attic / OpenROAD-Utilities
  Open-sourced utilities for initial flow setup, calibration, and other user functions for OpenROAD project
  ☆19Updated 5 years ago
• rachelselinar / DREAMPlaceFPGA
  An Open-Source Analytical Placer for Large Scale Heterogeneous FPGAs using Deep-Learning Toolkit
  ☆79Updated last month