hsluoyz / AtalantaLinks
Atalanta is a modified ATPG (Automatic Test Pattern Generation) tool and fault simulator, orginally from VirginiaTech University.
☆83Updated last year
Alternatives and similar repositories for Atalanta
Users that are interested in Atalanta are comparing it to the libraries listed below
Sorting:
- FAN (fan-out-oriented) ATPG (Automatic Test Pattern Generation) and Fault Simulation command line tool☆94Updated 2 months ago
- A Standalone Structural Verilog Parser☆97Updated 3 years ago
- ASIC Design Kit for FreePDK45 + Nangate for use with mflowgen☆186Updated 5 years ago
- ☆188Updated 6 months ago
- Open Source tool to build liberty files and for Characterizing Standard Cells.☆27Updated 4 years ago
- A complete open-source design-for-testing (DFT) Solution☆164Updated 3 weeks ago
- ☆105Updated 5 years ago
- An Open-Source Analytical Placer for Large Scale Heterogeneous FPGAs using Deep-Learning Toolkit☆84Updated 4 months ago
- Collection of digital hardware modules & projects (benchmarks)☆61Updated last week
- IDEA project source files☆108Updated last month
- AutoSVA is a tool to automatically generate formal testbenches for unit-level RTL verification. The goal is to, based on annotations made…☆89Updated last year
- Introductory course into static timing analysis (STA).☆97Updated 2 months ago
- ☆44Updated last year
- ☆172Updated 4 years ago
- ☆86Updated this week
- This repository is dedicated to providing a comprehensive guide and practical examples for using VC Formal for formal verification. Our g…☆37Updated last year
- A parser for Value Change Dump (VCD) files as specified in the IEEE System Verilog 1800-2012 standard.☆100Updated 3 years ago
- A collection of ISCAS,ITC,TAU and other Benchmark Circuits for EDA tool evaluation.☆56Updated 8 months ago
- EDA physical synthesis optimization kit☆61Updated last year
- ☆45Updated last year
- This is a tutorial on standard digital design flow☆79Updated 4 years ago
- EPFL and ISCAS85 combinational benchmark circuits in generic gate verilog☆28Updated 5 years ago
- Verilog parser, preprocessor, and related tools for the Verilog-Perl package☆139Updated last year
- Logic synthesis and ABC based optimization☆49Updated 2 weeks ago
- mflowgen -- A Modular ASIC/FPGA Flow Generator☆264Updated 3 weeks ago
- This repository has a list of collaterals needed for ICC2 workshop. It has a modified version of raven_soc which was taped-out by Efables…☆37Updated 5 years ago
- Standard Cell Library based Memory Compiler using FF/Latch cells☆156Updated 2 months ago
- AMF-Placer 2.0: An open-source timing-driven analytical mixed-size FPGA placer of heterogeneous resources (LUT/FF/LUTRAM/MUX/CARRY/DSP/BR…☆105Updated last year
- AMC: Asynchronous Memory Compiler☆50Updated 5 years ago
- reference block design for the ASAP7nm library in Cadence Innovus☆51Updated last year