Alternatives and similar repositories for Atalanta

Users that are interested in Atalanta are comparing it to the libraries listed below

• OpenTimer / Parser-Verilog
  A Standalone Structural Verilog Parser
  ☆99Updated 3 years ago
• ispras / hdl-benchmarks
  Collection of digital hardware modules & projects (benchmarks)
  ☆74Updated last week
• NTU-LaDS-II / FAN_ATPG
  FAN (fan-out-oriented) ATPG (Automatic Test Pattern Generation) and Fault Simulation command line tool
  ☆103Updated 5 months ago
• PrincetonUniversity / AutoSVA
  AutoSVA is a tool to automatically generate formal testbenches for unit-level RTL verification. The goal is to, based on annotations made…
  ☆95Updated last year
• AUCOHL / Fault
  A complete open-source design-for-testing (DFT) Solution
  ☆171Updated 3 months ago
• pkuzjx / eda-collection
  ☆107Updated 6 years ago
• The-OpenROAD-Project / asap7
  ☆216Updated 9 months ago
• brabect1 / sta_basics_course
  Introductory course into static timing analysis (STA).
  ☆99Updated 5 months ago
• bojackchen / digital-flow
  This is a tutorial on standard digital design flow
  ☆79Updated 4 years ago
• lnis-uofu / LSOracle
  IDEA project source files
  ☆110Updated last month
• Ghonimo / Formal-Verification-With-VC-Formal--Tutorials-and-Examples
  This repository is dedicated to providing a comprehensive guide and practical examples for using VC Formal for formal verification. Our g…
  ☆42Updated last year
• parallaxsw / OpenSTA
  ☆95Updated this week
• jpsety / verilog_benchmark_circuits
  EPFL and ISCAS85 combinational benchmark circuits in generic gate verilog
  ☆29Updated 5 years ago
• santoshsmalagi / Benchmarks
  A collection of ISCAS,ITC,TAU and other Benchmark Circuits for EDA tool evaluation.
  ☆58Updated 11 months ago
• HKUSTGZ-MICS-LYU / FlattenRTL
  This is a python repo for flattening Verilog
  ☆20Updated 7 months ago
• cornell-brg / pymtl3-net
  Project repo for the POSH on-chip network generator
  ☆52Updated 8 months ago
• ben-marshall / verilog-vcd-parser
  A parser for Value Change Dump (VCD) files as specified in the IEEE System Verilog 1800-2012 standard.
  ☆102Updated 3 years ago
• vaughnbetz / COFFE
  ☆45Updated last year
• spider-tronix / Standard-Cell-Characterization
  Open Source tool to build liberty files and for Characterizing Standard Cells.
  ☆28Updated 4 years ago
• veripool / verilog-perl
  Verilog parser, preprocessor, and related tools for the Verilog-Perl package
  ☆144Updated last year
• mflowgen / freepdk-45nm
  ASIC Design Kit for FreePDK45 + Nangate for use with mflowgen
  ☆193Updated 5 years ago
• fvutils / pyvsc
  Python packages providing a library for Verification Stimulus and Coverage
  ☆131Updated 3 weeks ago
• csail-csg / pyverilator
  Python wrapper for verilator model
  ☆92Updated last year
• scale-lab / OpenPhySyn
  EDA physical synthesis optimization kit
  ☆63Updated 2 years ago
• rachelselinar / DREAMPlaceFPGA
  An Open-Source Analytical Placer for Large Scale Heterogeneous FPGAs using Deep-Learning Toolkit
  ☆88Updated 7 months ago
• hkust-zhiyao / MasterRTL
  MasterRTL: A Pre-Synthesis PPA Estimation Framework for Any RTL Design
  ☆59Updated 6 months ago
• asyncvlsi / AMC
  AMC: Asynchronous Memory Compiler
  ☆51Updated 5 years ago
• limerainne / Dockerize-EDA
  [WIP] Dockerize Synopsys/Cadence EDA tools
  ☆93Updated 6 years ago
• AmeerAbdelhadi / Multiported-RAM
  Modular Multi-ported SRAM-based Memory
  ☆31Updated last year
• cad-polito-it / I99T
  ITC'99 benchmarks developed in the CAD Group at Politecnico di Torino
  ☆66Updated 7 months ago