gsmecher / minimax
Minimax: a Compressed-First, Microcoded RISC-V CPU
☆214Updated last year
Alternatives and similar repositories for minimax
Users that are interested in minimax are comparing it to the libraries listed below
Sorting:
- Glacial - microcoded RISC-V core designed for low FPGA resource utilization☆84Updated 5 years ago
- CoreScore☆151Updated 3 months ago
- 😎 A curated list of awesome RISC-V implementations☆135Updated 2 years ago
- A configurable RTL to bitstream FPGA toolchain☆33Updated last week
- A configurable and approachable tool for FPGA debugging and rapid prototyping.☆135Updated last month
- Create fast and efficient standard cell based adders, multipliers and multiply-adders.☆114Updated last year
- Design digital circuits in C. Simulate really fast with a regular compiler.☆173Updated 2 years ago
- SoC based on VexRiscv and ICE40 UP5K☆158Updated last month
- 4 stage, in-order, secure RISC-V core based on the CV32E40P☆145Updated 6 months ago
- Documenting Lattice's 28nm FPGA parts☆142Updated last year
- Linux capable RISC-V SoC designed to be readable and useful.☆143Updated 3 weeks ago
- User-friendly explanation of Yosys options☆113Updated 3 years ago
- Experimental flows using nextpnr for Xilinx devices☆234Updated 7 months ago
- VHDL synthesis (based on ghdl)☆334Updated 3 weeks ago
- Exploring gate level simulation☆57Updated 3 weeks ago
- Naive Educational RISC V processor☆83Updated 7 months ago
- Instruction set simulator for RISC-V, MIPS and ARM-v6m☆97Updated 3 years ago
- ⛔ DEPRECATED ⛔ Lean but mean RISC-V system!☆223Updated last year
- ☆78Updated last year
- System on Chip toolkit for Amaranth HDL☆89Updated 7 months ago
- PCIe Endpoint on Xilinx 7-Series FPGAs with the PCIE_2_1 hard block and GTP transceivers☆39Updated 2 weeks ago
- Example LED blinking project for your FPGA dev board of choice☆175Updated 2 months ago
- Small footprint and configurable DRAM core☆413Updated last week
- A pipelined RISC-V processor☆55Updated last year
- Small footprint and configurable Ethernet core☆237Updated 3 weeks ago
- ☆41Updated 4 years ago
- RISC-V RV64GC emulator designed for RTL co-simulation☆229Updated 5 months ago
- CORE-V Wally is a configurable RISC-V Processor associated with RISC-V System-on-Chip Design textbook. Contains a 5-stage pipeline, suppo…☆371Updated this week
- 4 stage, in-order, compute RISC-V core based on the CV32E40P☆235Updated 6 months ago
- A minimal-area RISC-V core with a scalable data path to 1, 2, 4, or 8 bits and manifold variants.☆91Updated 8 months ago