Alternatives and similar repositories for minimax

Users that are interested in minimax are comparing it to the libraries listed below

• siliconcompiler / logik
  A configurable RTL to bitstream FPGA toolchain
  ☆35Updated 2 weeks ago
• drom / awesome-riscv
  😎 A curated list of awesome RISC-V implementations
  ☆136Updated 2 years ago
• olofk / corescore
  CoreScore
  ☆155Updated 4 months ago
• regymm / quasiSoC
  Linux capable RISC-V SoC designed to be readable and useful.
  ☆143Updated last week
• YosysHQ / nerv
  Naive Educational RISC V processor
  ☆83Updated this week
• fusesoc / blinky
  Example LED blinking project for your FPGA dev board of choice
  ☆175Updated last week
• brouhaha / glacial
  Glacial - microcoded RISC-V core designed for low FPGA resource utilization
  ☆84Updated 5 years ago
• fischermoseley / manta
  A configurable and approachable tool for FPGA debugging and rapid prototyping.
  ☆136Updated last month
• openhwgroup / cv32e40s
  4 stage, in-order, secure RISC-V core based on the CV32E40P
  ☆146Updated 7 months ago
• gatecat / nextpnr-xilinx
  Experimental flows using nextpnr for Xilinx devices
  ☆237Updated 7 months ago
• suarezvictor / CflexHDL
  Design digital circuits in C. Simulate really fast with a regular compiler.
  ☆173Updated 2 years ago
• sylefeb / Silixel
  Exploring gate level simulation
  ☆58Updated last month
• SpinalHDL / SaxonSoc
  SoC based on VexRiscv and ICE40 UP5K
  ☆158Updated 2 months ago
• enjoy-digital / litedram
  Small footprint and configurable DRAM core
  ☆415Updated last week
• Ravenslofty / yosys-cookbook
  User-friendly explanation of Yosys options
  ☆113Updated 3 years ago
• chipsalliance / dromajo
  RISC-V RV64GC emulator designed for RTL co-simulation
  ☆229Updated 6 months ago
• pulp-platform / snitch
  ⛔ DEPRECATED ⛔ Lean but mean RISC-V system!
  ☆224Updated last year
• gatecat / prjoxide
  Documenting Lattice's 28nm FPGA parts
  ☆143Updated last year
• openhwgroup / core-v-cores
  CORE-V Family of RISC-V Cores
  ☆269Updated 3 months ago
• zylin / zpu
  The Zylin ZPU
  ☆243Updated 10 years ago
• Domipheus / RPU
  Basic RISC-V CPU implementation in VHDL.
  ☆165Updated 4 years ago
• openhwgroup / cvw
  CORE-V Wally is a configurable RISC-V Processor associated with RISC-V System-on-Chip Design textbook. Contains a 5-stage pipeline, suppo…
  ☆381Updated this week
• ZipCPU / autofpga
  A utility for Composing FPGA designs from Peripherals
  ☆179Updated 5 months ago
• olofk / vidbo
  Virtual Development Board
  ☆60Updated 3 years ago
• antonblanchard / vlsiffra
  Create fast and efficient standard cell based adders, multipliers and multiply-adders.
  ☆114Updated last year
• chipsalliance / f4pga-examples
  Example designs showing different ways to use F4PGA toolchains.
  ☆276Updated last year
• pieter3d / simview
  ☆79Updated last year
• tenstorrent / riscv-ocelot
  Ocelot: The Berkeley Out-of-Order Machine With V-EXT support
  ☆165Updated 4 months ago
• openhwgroup / programs
  Documentation for the OpenHW Group's set of CORE-V RISC-V cores
  ☆214Updated last week
• minerva-cpu / minerva
  A 32-bit RISC-V soft processor
  ☆311Updated 3 months ago