gsmecher / minimaxView external linksLinks
Minimax: a Compressed-First, Microcoded RISC-V CPU
☆224Apr 21, 2024Updated last year
Alternatives and similar repositories for minimax
Users that are interested in minimax are comparing it to the libraries listed below
Sorting:
- VRoom! RISC-V CPU☆516Sep 2, 2024Updated last year
- Linux capable RISC-V SoC designed to be readable and useful.☆158Dec 19, 2025Updated last month
- SERV - The SErial RISC-V CPU☆1,751Updated this week
- Gateware / Firmware / BuildRoot to run linux on iCE40 / iCEBreaker☆103Feb 17, 2023Updated 2 years ago
- A minimal-area RISC-V core with a scalable data path to 1, 2, 4, or 8 bits and manifold variants.☆111Feb 3, 2026Updated last week
- Silice is an easy-to-learn, powerful hardware description language, that simplifies designing hardware algorithms with parallelism and pi…☆1,396Jan 5, 2026Updated last month
- 32-bit RISC-V system on chip for iCE40 FPGAs☆313May 25, 2023Updated 2 years ago
- FLIX-V: FPGA, Linux and RISC-V☆42Nov 5, 2023Updated 2 years ago
- ☆33Nov 25, 2022Updated 3 years ago
- Doom classic port to lightweight RISC‑V☆107Jul 25, 2022Updated 3 years ago
- RISC-V processor with CPI=1 (every single instruction executed in a single clock cycle).☆22Feb 4, 2026Updated last week
- ☆306Jan 23, 2026Updated 3 weeks ago
- Single/Multi-channel Full Speed USB interface for FPGA and ASIC designs☆187Mar 10, 2024Updated last year
- A pipelined RISC-V processor☆63Dec 1, 2023Updated 2 years ago
- Documenting Lattice's 28nm FPGA parts☆148Jan 26, 2026Updated 2 weeks ago
- Dual-issue RV64IM processor for fun & learning☆64Jul 4, 2023Updated 2 years ago
- ✔️ Port of RISCOF to check NEORV32 for RISC-V ISA compatibility.☆38Feb 3, 2026Updated last week
- An attempt to recreate the RP2040 PIO in an FPGA☆309Jun 6, 2024Updated last year
- Some materials and sample source for RV32 OS projects.☆21May 31, 2022Updated 3 years ago
- Snapshot of the April 2000 XSOC/xr16 Project Beta 0.93, collateral for Jan Gray's series "Building a RISC System in an FPGA" published in…☆12Jan 7, 2023Updated 3 years ago
- Nitro USB FPGA core☆86Mar 6, 2024Updated last year
- Simple RISC-V processor for FPGAs☆21Apr 18, 2023Updated 2 years ago
- Proposed RISC-V Composable Custom Extensions Specification☆70Jun 28, 2025Updated 7 months ago
- Learning FPGA, yosys, nextpnr, and RISC-V☆3,392Nov 18, 2025Updated 2 months ago
- Turbo9 - Pipelined 6809 Microprocessor IP☆160Dec 5, 2025Updated 2 months ago
- Glacial - microcoded RISC-V core designed for low FPGA resource utilization☆88Oct 29, 2019Updated 6 years ago
- Another size-optimized RISC-V CPU for your consideration.☆59Feb 1, 2026Updated 2 weeks ago
- shdl6800: A 6800 processor written in SpinalHDL☆25Jan 12, 2020Updated 6 years ago
- A C-like hardware description language (HDL) adding high level synthesis(HLS)-like automatic pipelining as a language construct/compiler …☆697Updated this week
- J-Core J2/J32 5 stage pipeline CPU core☆61Nov 24, 2020Updated 5 years ago
- Create fast and efficient standard cell based adders, multipliers and multiply-adders.☆120Sep 20, 2023Updated 2 years ago
- A tiny Open POWER ISA softcore written in VHDL 2008☆710Feb 4, 2026Updated last week
- ☆20May 8, 2025Updated 9 months ago
- Basic USB 1.1 Host Controller for small FPGAs☆97Jun 6, 2020Updated 5 years ago
- BRISKI ( Barrel RISC-V for Kilo-core Implementations ) is a fast and compact RISC-V barrel processor core that emphasize high throughput …☆29Nov 28, 2025Updated 2 months ago
- Code for Bruno Levy's learn-fpga tutorial written in Amaranth HDL☆112Jul 20, 2024Updated last year
- Virtual development board for HDL design☆42Mar 31, 2023Updated 2 years ago
- An Open Source Link Protocol and Controller☆29Jul 26, 2021Updated 4 years ago
- CORE-V Wally is a configurable RISC-V Processor associated with RISC-V System-on-Chip Design textbook. Contains a 5-stage pipeline, suppo…☆483Updated this week