Alternatives and similar repositories for minimax

Users that are interested in minimax are comparing it to the libraries listed below

• drom / awesome-riscv
  😎 A curated list of awesome RISC-V implementations
  ☆138Updated 2 years ago
• olofk / corescore
  CoreScore
  ☆167Updated 3 weeks ago
• brouhaha / glacial
  Glacial - microcoded RISC-V core designed for low FPGA resource utilization
  ☆87Updated 6 years ago
• siliconcompiler / logik
  A configurable RTL to bitstream FPGA toolchain
  ☆54Updated last week
• suarezvictor / CflexHDL
  Design digital circuits in C. Simulate really fast with a regular compiler.
  ☆173Updated this week
• stnolting / neoTRNG
  🎲 A Tiny and Platform-Independent True Random Number Generator for any FPGA (and ASIC).
  ☆205Updated 2 months ago
• regymm / pcie_7x
  PCIe Endpoint on Xilinx 7-Series FPGAs with the PCIE_2_1 hard block and GTP transceivers
  ☆62Updated 6 months ago
• fischermoseley / manta
  A configurable and approachable tool for FPGA debugging and rapid prototyping.
  ☆142Updated 7 months ago
• regymm / quasiSoC
  Linux capable RISC-V SoC designed to be readable and useful.
  ☆152Updated 5 months ago
• fusesoc / blinky
  Example LED blinking project for your FPGA dev board of choice
  ☆186Updated last month
• JulianKemmerer / PipelineC-Graphics
  Graphics demos
  ☆112Updated last year
• gatecat / nextpnr-xilinx
  Experimental flows using nextpnr for Xilinx devices
  ☆245Updated last year
• MoonbaseOtago / vroom
  VRoom! RISC-V CPU
  ☆512Updated last year
• gatecat / prjoxide
  Documenting Lattice's 28nm FPGA parts
  ☆144Updated last year
• Domipheus / RPU
  Basic RISC-V CPU implementation in VHDL.
  ☆171Updated 5 years ago
• enjoy-digital / liteeth
  Small footprint and configurable Ethernet core
  ☆268Updated this week
• pulp-platform / snitch
  ⛔ DEPRECATED ⛔ Lean but mean RISC-V system!
  ☆226Updated last year
• minerva-cpu / minerva
  A 32-bit RISC-V soft processor
  ☆316Updated 3 months ago
• mosscomp / moss
  A computer for human beings.
  ☆47Updated last year
• zylin / zpu
  The Zylin ZPU
  ☆244Updated 10 years ago
• YosysHQ / nerv
  Naive Educational RISC V processor
  ☆90Updated last month
• amaranth-lang / amaranth-boards
  Board definitions for Amaranth HDL
  ☆121Updated 2 months ago
• lawrie / fpga_pio
  An attempt to recreate the RP2040 PIO in an FPGA
  ☆305Updated last year
• openpower-cores / a2i
  ☆247Updated 3 years ago
• SpinalHDL / SaxonSoc
  SoC based on VexRiscv and ICE40 UP5K
  ☆158Updated 7 months ago
• Ravenslofty / yosys-cookbook
  User-friendly explanation of Yosys options
  ☆112Updated 4 years ago
• JulianKemmerer / PipelineC
  A C-like hardware description language (HDL) adding high level synthesis(HLS)-like automatic pipelining as a language construct/compiler …
  ☆683Updated this week
• howerj / bit-serial
  A bit-serial CPU written in VHDL, with a simulator written in C.
  ☆133Updated last year
• mnemocron / my-discrete-fpga
  My own FPGA architecture simulated in VHDL, realized with 7400-logic on PCB.
  ☆45Updated last year
• sylefeb / Silixel
  Exploring gate level simulation
  ☆58Updated 6 months ago