souravsanyal06 / DNN-Dataflow-simulatorLinks
Implementation of Input Stationary, Weight Stationary and Output Stationary dataflow for given neural network on a tiled architecture
☆9Updated 5 years ago
Alternatives and similar repositories for DNN-Dataflow-simulator
Users that are interested in DNN-Dataflow-simulator are comparing it to the libraries listed below
Sorting:
- ☆18Updated 2 years ago
- [DATE 2025] Official implementation and dataset of AIrchitect v2: Learning the Hardware Accelerator Design Space through Unified Represen…☆15Updated 6 months ago
- [ICASSP'20] DNN-Chip Predictor: An Analytical Performance Predictor for DNN Accelerators with Various Dataflows and Hardware Architecture…☆25Updated 2 years ago
- A general framework for optimizing DNN dataflow on systolic array☆39Updated 4 years ago
- Here are some implementations of basic hardware units in RTL language (verilog for now), which can be used for area/power evaluation and …☆11Updated last year
- ☆71Updated 2 years ago
- A systolic array simulator for multi-cycle MACs and varying-byte words, with the paper accepted to HPCA 2022.☆79Updated 3 years ago
- Designs for finalist teams of the DAC System Design Contest☆37Updated 5 years ago
- A bit-level sparsity-awared multiply-accumulate process element.☆16Updated last year
- ☆12Updated last year
- MICRO22 artifact evaluation for Sparseloop☆45Updated 2 years ago
- dMazeRunner: Dataflow acceleration optimization infrastructure for coarse-grained programmable accelerators☆45Updated 3 years ago
- Benchmark framework of compute-in-memory based accelerators for deep neural network (inference engine focused)☆22Updated 4 years ago
- A Reconfigurable Accelerator with Data Reordering Support for Low-Cost On-Chip Dataflow Switching☆55Updated 3 months ago
- Fast Emulation of Approximate DNN Accelerators in PyTorch☆23Updated last year
- ☆35Updated 5 years ago
- Open-source of MSD framework☆16Updated last year
- An FPGA accelerator for general-purpose Sparse-Matrix Dense-Matrix Multiplication (SpMM).☆81Updated 11 months ago
- ☆33Updated 6 years ago
- [TCAD'23] AccelTran: A Sparsity-Aware Accelerator for Transformers☆49Updated last year
- ☆17Updated 2 months ago
- ☆71Updated 5 years ago
- A Unified Framework for Training, Mapping and Simulation of ReRAM-Based Convolutional Neural Network Acceleration☆34Updated 3 years ago
- HLS implemented systolic array structure☆41Updated 7 years ago
- Linux docker for the DNN accelerator exploration infrastructure composed of Accelergy and Timeloop☆54Updated 3 months ago
- ☆28Updated 2 years ago
- [TECS'23] A project on the co-design of Accelerators and CNNs.☆20Updated 2 years ago
- ☆27Updated 3 months ago
- A framework for fast exploration of the depth-first scheduling space for DNN accelerators☆39Updated 2 years ago
- ☆16Updated 2 years ago