LeiWang1999 / nvdla_loadables

Related projects ⓘ

Alternatives and complementary repositories for nvdla_loadables

• zeasa / nvdla-compiler
  ☆42Updated 4 years ago
• THU-DSP-LAB / ventus-gpgpu-isa-simulator
  Ventus GPGPU ISA Simulator Based on Spike
  ☆37Updated 2 weeks ago
• WuDan0399 / Integrate-NVDLA-and-TVM
  ☆30Updated last year
• THU-DSP-LAB / ventus-gpgpu-cpp-simulator
  Cycle-accurate C++ & SystemC simulator for the RISC-V GPGPU Ventus
  ☆19Updated 3 months ago
• JunningWu / AIChip
  Aiming at an AI Chip based on RISC-V and NVDLA.
  ☆21Updated 6 years ago
• prasshantg / personal
  ☆16Updated 5 years ago
• LeiWang1999 / nvdla-parser
  A NVDLA Loadable Parser.
  ☆10Updated 2 years ago
• VVViy / VVViy.github.io
  This is Max's blog, something interesting in it.
  ☆13Updated last year
• isuckatdrifting / Zeus
  NVDLA small config implementation on Zynq ZCU104 (evaluation)
  ☆23Updated 5 years ago
• meton-robean / Vector_MulAdd_Accelerator
  vector multiplication adder accelerator (using chisel 3 and RocketChip RoCC ) 向量乘法累加加速器
  ☆49Updated 4 years ago
• DPCEKY / systolic-array
  HLS implemented systolic array structure
  ☆40Updated 6 years ago
• soDLA-publishment / somnia
  Learn NVDLA by SOMNIA
  ☆26Updated 4 years ago
• pulp-platform / fpu
  ☆37Updated 5 years ago
• suchandler96 / gem5-NVDLA
  ☆21Updated last month
• DNN-Accelerators / Open-Source-IPs
  ☆32Updated 5 years ago
• icubecorp / nvdla_compiler
  ☆21Updated 6 years ago
• openasic-org / xkDLA
  xkDLA：XinKai Deep Learning Accelerator (RTL)
  ☆25Updated 9 months ago
• sharc-lab / FPGA_ECE8893
  ☆29Updated 2 months ago
• williamyang4978 / PipeCNN_Winograd
  An OpenCL-Based FPGA Accelerator for Compressed YOLOv2
  ☆36Updated 3 years ago
• natu4u / GSOC_TensorCore
  TensorCore Vector Processor for Deep Learning - Google Summer of Code Project
  ☆21Updated 3 years ago
• cwfletcher / buffets
  Implementations of Buffets, which are efficient, composable idioms for implementing Explicit Decoupled Data Orchestration.
  ☆63Updated 5 years ago
• comparch-security / spike-cache
  Spike with a coherence supported cache model
  ☆12Updated 4 months ago
• hngenc / systolic-array
  A DSL for Systolic Arrays
  ☆78Updated 5 years ago
• microideax / Open-Dnn
  ☆27Updated 5 years ago
• rgb000000 / eyeriss-chisel3
  eyeriss-chisel3
  ☆38Updated 2 years ago
• THU-DSP-LAB / ventus-gpgpu-verilog
  GPGPU supporting RISCV-V, developed with verilog HDL
  ☆68Updated 2 months ago
• wzc810049078 / systolic-array-matrix-multiplier
  A systolic array matrix multiplier
  ☆23Updated 5 years ago
• XUANTIE-RV / riscv-matrix-extension-spec
  A matrix extension proposal for AI applications under RISC-V architecture
  ☆106Updated 2 weeks ago
• jgoeders / dac_sdc_2020_designs
  Designs for finalist teams of the DAC System Design Contest
  ☆35Updated 4 years ago