LeiWang1999 / nvdla_loadables
some sample caffemodel, prototxt, test images and pre compiled loadabes .
☆12Updated 3 years ago
Alternatives and similar repositories for nvdla_loadables:
Users that are interested in nvdla_loadables are comparing it to the libraries listed below
- ☆42Updated 5 years ago
- A NVDLA Loadable Parser.☆10Updated 2 years ago
- ☆30Updated last year
- Aiming at an AI Chip based on RISC-V and NVDLA.☆20Updated 6 years ago
- ☆16Updated 5 years ago
- ☆24Updated 4 months ago
- HLS implemented systolic array structure☆41Updated 7 years ago
- vector multiplication adder accelerator (using chisel 3 and RocketChip RoCC ) 向量乘法累加加速器☆51Updated 4 years ago
- 记录阅读各类paper的想法笔记(关注体系结构,机器学习系统,深度学习,计算机视觉)☆24Updated 5 years ago
- Cycle-accurate C++ & SystemC simulator for the RISC-V GPGPU Ventus☆21Updated 6 months ago
- RocketChip RoCC Accelerator template (Risc-V, Chisel )(加速器开发项目框架)☆13Updated 5 years ago
- Ventus GPGPU ISA Simulator Based on Spike☆39Updated 2 weeks ago
- Implementations of Buffets, which are efficient, composable idioms for implementing Explicit Decoupled Data Orchestration.☆66Updated 5 years ago
- A DSL for Systolic Arrays☆78Updated 6 years ago
- Learn NVDLA by SOMNIA☆30Updated 5 years ago
- ☆33Updated this week
- agile hardware-software co-design☆47Updated 3 years ago
- Code for paper "FuSeConv Fully Separable Convolutions for Fast Inference on Systolic Arrays" published at DATE 2021☆14Updated 3 years ago
- cycle accurate Network-on-Chip Simulator☆25Updated last year
- Hands-on experience programming AI Engines using Vitis Unified Software Platform☆38Updated 6 months ago
- Spike with a coherence supported cache model☆14Updated 6 months ago
- ☆33Updated 5 years ago
- Multi-core HW accelerator mapping optimization framework for layer-fused ML workloads.☆47Updated this week
- mNPUsim: A Cycle-accurate Multi-core NPU Simulator (IISWC 2023)☆44Updated last month
- Linux docker for the DNN accelerator exploration infrastructure composed of Accelergy and Timeloop☆47Updated last week
- Release of stream-specialization software/hardware stack.☆120Updated last year
- ☆15Updated 3 years ago
- TVM for chips base on Xuantie CPU, an open deep learning compiler stack.☆30Updated 7 months ago
- An LLVM pass that can generate CDFG and map the target loops onto a parameterizable CGRA.☆59Updated 2 months ago
- Automatic generation of FPGA-based learning accelerators for the neural network family☆60Updated 5 years ago