☆49Nov 18, 2019Updated 6 years ago
Alternatives and similar repositories for nvdla-compiler
Users that are interested in nvdla-compiler are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- A NVDLA Loadable Parser.☆13Mar 2, 2022Updated 4 years ago
- This is Max's blog, something interesting in it.☆13Jan 1, 2023Updated 3 years ago
- some sample caffemodel, prototxt, test images and pre compiled loadabes .☆14Apr 30, 2021Updated 5 years ago
- NVDLA is an Open source DL/ML accelerator, which is very suitable for individuals or college students. This is the NOTES when I learn and…☆232Dec 18, 2018Updated 7 years ago
- Learn NVDLA by SOMNIA☆42Dec 13, 2019Updated 6 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- ☆17Oct 2, 2019Updated 6 years ago
- Chisel implementation of the NVIDIA Deep Learning Accelerator (NVDLA), with self-driving accelerated☆237Dec 22, 2025Updated 7 months ago
- Express DLA implementation for FPGA, revised based on NVDLA.☆12Oct 17, 2019Updated 6 years ago
- NVDLA (An Opensource DL Accelerator Framework) implementation on FPGA.☆390Dec 27, 2023Updated 2 years ago
- FireSim-NVDLA: NVIDIA Deep Learning Accelerator (NVDLA) Integrated with RISC-V Rocket Chip SoC Running on the Amazon FPGA Cloud☆166Jan 16, 2022Updated 4 years ago
- A discussion group on Open Source Deep Learning Accelerator, with technical reports and potential hardware/software issues.☆146Nov 16, 2017Updated 8 years ago
- ☆41Oct 26, 2021Updated 4 years ago
- ☆33Mar 6, 2023Updated 3 years ago
- OpenDLA for trying the demo and FPGA solution☆17Jul 28, 2022Updated 4 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- Open Neural Network Compiler☆532Aug 22, 2023Updated 2 years ago
- Matrix Accelerator Generator for GeMM Operations based on SIGMA Architecture in CHISEL HDL☆15Mar 21, 2024Updated 2 years ago
- ☆61Mar 14, 2022Updated 4 years ago
- ☆22Oct 15, 2018Updated 7 years ago
- ☆46Mar 31, 2025Updated last year
- A Reconfigurable Accelerator for Deep Convolutional Neural Networks Implemented by Chisel3.☆29Jul 14, 2021Updated 5 years ago
- Deep Learning Accelerator Based on Eyeriss V2 Architecture with custom RISC-V extended instructions☆210Jun 25, 2020Updated 6 years ago
- An optimized neural network operator library for chips base on Xuantie CPU.☆103Feb 10, 2026Updated 5 months ago
- Hardware acceleration for transformer attention mechanisms on NVIDIA Deep Learning Accelerator (NVDLA), enabling efficient inference of…☆17Mar 30, 2025Updated last year
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- This is a general-purpose simulator for unary computing based on PyTorch, with the paper accepted to ISCA 2020 and awarded IEEE Micro Top…☆47Jul 31, 2025Updated 11 months ago
- PyMTL3 wrapper of the Berkeley Hardfloat IP☆10Aug 9, 2023Updated 2 years ago
- A systolic array simulator for multi-cycle MACs and varying-byte words, with the paper accepted to HPCA 2022.☆84Nov 7, 2021Updated 4 years ago
- ☆20Feb 9, 2020Updated 6 years ago
- NVDLA SW☆519Jan 28, 2021Updated 5 years ago
- Virtual Platform for NVDLA☆168Aug 23, 2018Updated 7 years ago
- A SystemVerilog implementation of Row-Stationary dataflow and Hierarchical Mesh Network-on-Chip Architecture based on Eyeriss CNN Acceler…☆184Dec 14, 2019Updated 6 years ago
- Accelerate multihead attention transformer model using HLS for FPGA☆13Dec 7, 2023Updated 2 years ago
- SystemC Configuration, Control and Inspection (CCI)☆22Jul 7, 2026Updated 3 weeks ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- Caffe models for use with MIPS Atlas ARC® EV processors☆46May 8, 2024Updated 2 years ago
- ☆47Aug 23, 2023Updated 2 years ago
- Timeloop performs modeling, mapping and code-generation for tensor algebra workloads on various accelerator architectures.☆506Updated this week
- Backup: Library implementing a C TLM-2 style to bridge C models to SystemC TLM-2.0 (C++) from GreenSocs (https://git.greensocs.com/tlm/tl…☆19Aug 13, 2018Updated 7 years ago
- ☆74Feb 16, 2023Updated 3 years ago
- MICRO22 artifact evaluation for Sparseloop☆48Aug 8, 2022Updated 3 years ago
- Linear algebra accelerators for RISC-V (published in ICCD 17)☆66Oct 5, 2017Updated 8 years ago