Alternatives and similar repositories for Integrate-NVDLA-and-TVM:

Users that are interested in Integrate-NVDLA-and-TVM are comparing it to the libraries listed below

• zeasa / nvdla-compiler
  ☆44Updated 5 years ago
• JunningWu / AIChip
  Aiming at an AI Chip based on RISC-V and NVDLA.
  ☆20Updated 7 years ago
• suchandler96 / gem5-NVDLA
  ☆29Updated 2 weeks ago
• Accelergy-Project / accelergy-timeloop-infrastructure
  Linux docker for the DNN accelerator exploration infrastructure composed of Accelergy and Timeloop
  ☆52Updated 2 weeks ago
• LCAI-TIHU / SW
  LCAI-TIHU SW is a software stack of the AI inference processor based on RISC-V
  ☆23Updated 2 years ago
• THU-DSP-LAB / ventus-gpgpu-isa-simulator
  Ventus GPGPU ISA Simulator Based on Spike
  ☆43Updated last week
• tissue3 / EyerissSimulator
  Eyeriss chip simulator
  ☆36Updated 5 years ago
• union-codesign / union
  ☆14Updated 3 years ago
• soDLA-publishment / somnia
  Learn NVDLA by SOMNIA
  ☆33Updated 5 years ago
• GATECH-EIC / AutoDNNchip
  ☆70Updated 5 years ago
• prasshantg / personal
  ☆16Updated 5 years ago
• ucb-bar / onnxruntime-riscv
  Fork of upstream onnxruntime focused on supporting risc-v accelerators
  ☆84Updated 2 years ago
• maeri-project / MAERI_bsv
  MAERI: A DNN accelerator with reconfigurable interconnects to support flexible dataflow (http://synergy.ece.gatech.edu/tools/maeri/)
  ☆64Updated 3 years ago
• KULeuven-MICAS / DeFiNES
  A framework for fast exploration of the depth-first scheduling space for DNN accelerators
  ☆38Updated 2 years ago
• icubecorp / nvdla_compiler
  ☆21Updated 6 years ago
• MPSLab-ASU / dMazeRunner
  dMazeRunner: Dataflow acceleration optimization infrastructure for coarse-grained programmable accelerators
  ☆45Updated 3 years ago
• pku-liang / HASCO
  agile hardware-software co-design
  ☆46Updated 3 years ago
• sfu-arch / SpGEMM
  ☆35Updated 3 years ago
• harvard-acc / EdgeBERT
  HW/SW co-design of sentence-level energy optimizations for latency-aware multi-task NLP inference
  ☆46Updated last year
• DNN-Accelerators / Open-Source-IPs
  ☆33Updated 6 years ago
• PolyArch / dsa-framework
  Release of stream-specialization software/hardware stack.
  ☆120Updated last year
• SCLUO / ITRI-OpenDLA
  OpenDLA for trying the demo and FPGA solution
  ☆16Updated 2 years ago
• hngenc / stellar
  ☆26Updated 5 months ago
• jinhachung / tptpu-sim
  A Toy-Purpose TPU Simulator
  ☆18Updated 10 months ago
• cornell-zhang / HiSparse
  High-Performance Sparse Linear Algebra on HBM-Equipped FPGAs Using HLS
  ☆90Updated 6 months ago
• DPCEKY / systolic-array
  HLS implemented systolic array structure
  ☆41Updated 7 years ago
• PSAL-POSTECH / ONNXim
  ONNXim is a fast cycle-level simulator that can model multi-core NPUs for DNN inference
  ☆106Updated 2 months ago
• xuanyoya / Interstellar-CNN-scheduler
  Tool for optimize CNN blocking
  ☆94Updated 5 years ago
• harvard-acc / FlexASR
  FlexASR: A Reconfigurable Hardware Accelerator for Attention-based Seq-to-Seq Networks
  ☆42Updated last month
• Xilinx / mlir-air
  ☆93Updated last week