Alternatives and similar repositories for ITRI-OpenDLA

Users that are interested in ITRI-OpenDLA are comparing it to the libraries listed below

• soDLA-publishment / somnia
  Learn NVDLA by SOMNIA
  ☆36Updated 5 years ago
• zeasa / nvdla-compiler
  ☆46Updated 5 years ago
• VVViy / VVViy.github.io
  This is Max's blog, something interesting in it.
  ☆13Updated 2 years ago
• isuckatdrifting / Zeus
  NVDLA small config implementation on Zynq ZCU104 (evaluation)
  ☆23Updated 6 years ago
• jgoeders / dac_sdc_2020_designs
  Designs for finalist teams of the DAC System Design Contest
  ☆37Updated 5 years ago
• hlslibs / hls_tutorials
  Tutorials on HLS Design
  ☆52Updated 5 years ago
• natu4u / GSOC_TensorCore
  TensorCore Vector Processor for Deep Learning - Google Summer of Code Project
  ☆22Updated 3 years ago
• ac-optimus / Convolution-using-systolic-arrays
  ☆65Updated 6 years ago
• SameLight / ITRI-OpenDLA
  Express DLA implementation for FPGA, revised based on NVDLA.
  ☆9Updated 5 years ago
• DNN-Accelerators / Open-Source-IPs
  ☆34Updated 6 years ago
• DPCEKY / systolic-array
  HLS implemented systolic array structure
  ☆41Updated 7 years ago
• chenhaoc / cnnhwpe
  ☆66Updated 3 years ago
• PeterOgden / ZCU104_VideoDemo
  PYNQ demo as seen at FPL 2018
  ☆21Updated 4 years ago
• jiaaom / HPDLA
  Systolic-array based Deep Learning Accelerator generator
  ☆25Updated 4 years ago
• jgoeders / dac_sdc_2021
  ☆23Updated 3 years ago
• Caiyujie007 / OpenVPU
  This is an open CNN accelerator for everyone to use
  ☆14Updated 6 years ago
• ic-lab-duth / NoCpad
  HLS for Networks-on-Chip
  ☆35Updated 4 years ago
• pulp-platform / pulp-nn
  ☆83Updated last year
• romulus0914 / CNN_VGG19_verilog
  Convolution Neural Network of vgg19 model in verilog
  ☆49Updated 7 years ago
• tissue3 / EyerissSimulator
  Eyeriss chip simulator
  ☆36Updated 5 years ago
• gewuek / vitis_ai_custom_platform_flow
  This project is trying to create a base vitis platform to run with DPU
  ☆47Updated 5 years ago
• prasshantg / personal
  ☆16Updated 5 years ago
• lllibano / SystolicArray
  A parametric RTL code generator of an efficient integer MxM Systolic Array implementation for Xilinx FPGAs.
  ☆25Updated 3 months ago
• markcxli / FPGA_DPU
  This project is to implement YOLO v3 on Xilinx FPGA with DPU
  ☆59Updated 5 years ago
• CSL-KU / firesim-nvdla
  FireSim-NVDLA: NVIDIA Deep Learning Accelerator (NVDLA) Integrated with RISC-V Rocket Chip SoC Running on the Amazon FPGA Cloud
  ☆163Updated 3 years ago
• mfarhadi / CNNIOT
  ☆47Updated 7 years ago
• rgb000000 / eyeriss-chisel3
  eyeriss-chisel3
  ☆41Updated 3 years ago
• onioncc / iSmartDNN
  Light-weighted neural network inference for object detection on small-scale FPGA board
  ☆91Updated 6 years ago
• meton-robean / Vector_MulAdd_Accelerator
  vector multiplication adder accelerator (using chisel 3 and RocketChip RoCC ) 向量乘法累加加速器
  ☆53Updated 5 years ago
• suchandler96 / gem5-NVDLA
  ☆33Updated 4 months ago