Alternatives and similar repositories for ITRI-OpenDLA

Users that are interested in ITRI-OpenDLA are comparing it to the libraries listed below

• soDLA-publishment / somnia
  Learn NVDLA by SOMNIA
  ☆42Updated 6 years ago
• zeasa / nvdla-compiler
  ☆49Updated 6 years ago
• isuckatdrifting / Zeus
  NVDLA small config implementation on Zynq ZCU104 (evaluation)
  ☆24Updated 6 years ago
• WuDan0399 / Integrate-NVDLA-and-TVM
  ☆33Updated 2 years ago
• natu4u / GSOC_TensorCore
  TensorCore Vector Processor for Deep Learning - Google Summer of Code Project
  ☆24Updated 4 years ago
• DPCEKY / systolic-array
  HLS implemented systolic array structure
  ☆41Updated 8 years ago
• SameLight / ITRI-OpenDLA
  Express DLA implementation for FPGA, revised based on NVDLA.
  ☆11Updated 6 years ago
• suchandler96 / gem5-NVDLA
  ☆42Updated 10 months ago
• DNN-Accelerators / Open-Source-IPs
  ☆35Updated 6 years ago
• CSL-KU / firesim-nvdla
  FireSim-NVDLA: NVIDIA Deep Learning Accelerator (NVDLA) Integrated with RISC-V Rocket Chip SoC Running on the Amazon FPGA Cloud
  ☆165Updated 4 years ago
• jgoeders / dac_sdc_2020_designs
  Designs for finalist teams of the DAC System Design Contest
  ☆37Updated 5 years ago
• ac-optimus / Convolution-using-systolic-arrays
  ☆73Updated 7 years ago
• hlslibs / hls_tutorials
  Tutorials on HLS Design
  ☆51Updated 6 years ago
• pulp-platform / pulp-nn
  ☆89Updated 2 years ago
• jiaaom / HPDLA
  Systolic-array based Deep Learning Accelerator generator
  ☆28Updated 5 years ago
• chenhaoc / cnnhwpe
  ☆66Updated 3 years ago
• VVViy / VVViy.github.io
  This is Max's blog, something interesting in it.
  ☆13Updated 3 years ago
• rgb000000 / eyeriss-chisel3
  eyeriss-chisel3
  ☆40Updated 3 years ago
• ic-lab-duth / NoCpad
  HLS for Networks-on-Chip
  ☆39Updated 4 years ago
• lllibano / SystolicArray
  A parametric RTL code generator of an efficient integer MxM Systolic Array implementation for Xilinx FPGAs.
  ☆31Updated 5 months ago
• Caiyujie007 / OpenVPU
  This is an open CNN accelerator for everyone to use
  ☆14Updated 6 years ago
• bsc-loca / sauria
  SAURIA (Systolic-Array tensor Unit for aRtificial Intelligence Acceleration) is an open-source Convolutional Neural Network accelerator b…
  ☆82Updated 2 months ago
• Starrynightzyq / soNN
  A Reconfigurable Accelerator for Deep Convolutional Neural Networks Implemented by Chisel3.
  ☆29Updated 4 years ago
• nqHITSZ / Systolic-Array
  course design
  ☆23Updated 7 years ago
• pulp-platform / ITA
  ☆63Updated 9 months ago
• meton-robean / Vector_MulAdd_Accelerator
  vector multiplication adder accelerator (using chisel 3 and RocketChip RoCC ) 向量乘法累加加速器
  ☆53Updated 5 years ago
• tirumalnaidu / opencl-hls-cnn-accelerator
  OpenCL HLS based CNN Accelerator on Intel DE10 Nano FPGA.
  ☆82Updated 2 years ago
• DreamIP / haddoc2
  Caffe to VHDL
  ☆68Updated 5 years ago
• prasshantg / personal
  ☆16Updated 6 years ago
• JunningWu / AIChip
  Aiming at an AI Chip based on RISC-V and NVDLA.
  ☆21Updated 7 years ago