SCLUO / ITRI-OpenDLALinks
OpenDLA for trying the demo and FPGA solution
☆18Updated 3 years ago
Alternatives and similar repositories for ITRI-OpenDLA
Users that are interested in ITRI-OpenDLA are comparing it to the libraries listed below
Sorting:
- ☆46Updated 6 years ago
- Learn NVDLA by SOMNIA☆42Updated 5 years ago
- TensorCore Vector Processor for Deep Learning - Google Summer of Code Project☆23Updated 4 years ago
- Express DLA implementation for FPGA, revised based on NVDLA.☆11Updated 6 years ago
- NVDLA small config implementation on Zynq ZCU104 (evaluation)☆24Updated 6 years ago
- ☆33Updated 2 years ago
- ☆35Updated 6 years ago
- Designs for finalist teams of the DAC System Design Contest☆37Updated 5 years ago
- ☆71Updated 6 years ago
- Tutorials on HLS Design☆52Updated 5 years ago
- HLS implemented systolic array structure☆41Updated 8 years ago
- A parametric RTL code generator of an efficient integer MxM Systolic Array implementation for Xilinx FPGAs.☆27Updated 2 months ago
- course design☆23Updated 7 years ago
- Systolic-array based Deep Learning Accelerator generator☆27Updated 4 years ago
- This is Max's blog, something interesting in it.☆13Updated 2 years ago
- ☆23Updated 4 years ago
- This project is to implement YOLO v3 on Xilinx FPGA with DPU☆64Updated 5 years ago
- This is an open CNN accelerator for everyone to use☆14Updated 6 years ago
- SAURIA (Systolic-Array tensor Unit for aRtificial Intelligence Acceleration) is an open-source Convolutional Neural Network accelerator b…☆66Updated 2 weeks ago
- An HLS based winograd systolic CNN accelerator☆54Updated 4 years ago
- xkDLA:XinKai Deep Learning Accelerator (RTL)☆39Updated last year
- ☆86Updated 2 years ago
- eyeriss-chisel3☆40Updated 3 years ago
- This project implements a convolution kernel based on vivado HLS on zcu104☆37Updated 5 years ago
- HLS for Networks-on-Chip☆37Updated 4 years ago
- A Reconfigurable Accelerator for Deep Convolutional Neural Networks Implemented by Chisel3.☆29Updated 4 years ago
- Network on-Chip (NoC) simulator for simulating intra-chip data flow in Neural Network Accelerator☆34Updated last year
- ☆16Updated 6 years ago
- Binary Single Precision Floating-point Fused Multiply-Add Unit Design (Verilog HDL)☆22Updated 12 years ago
- Deep Learning Accelerator Based on Eyeriss V2 Architecture with custom RISC-V extended instructions☆204Updated 5 years ago