SCLUO / ITRI-OpenDLALinks
OpenDLA for trying the demo and FPGA solution
☆18Updated 3 years ago
Alternatives and similar repositories for ITRI-OpenDLA
Users that are interested in ITRI-OpenDLA are comparing it to the libraries listed below
Sorting:
- ☆49Updated 6 years ago
- Learn NVDLA by SOMNIA☆42Updated 6 years ago
- Designs for finalist teams of the DAC System Design Contest☆37Updated 5 years ago
- NVDLA small config implementation on Zynq ZCU104 (evaluation)☆24Updated 6 years ago
- TensorCore Vector Processor for Deep Learning - Google Summer of Code Project☆24Updated 4 years ago
- ☆33Updated 2 years ago
- This is an open CNN accelerator for everyone to use☆14Updated 6 years ago
- HLS implemented systolic array structure☆41Updated 8 years ago
- Express DLA implementation for FPGA, revised based on NVDLA.☆11Updated 6 years ago
- ☆23Updated 4 years ago
- ☆72Updated 7 years ago
- Tutorials on HLS Design☆52Updated 6 years ago
- This is Max's blog, something interesting in it.☆13Updated 3 years ago
- ☆35Updated 6 years ago
- RocketChip RoCC Accelerator template (Risc-V, Chisel )(加速器开发项目框架)☆15Updated 6 years ago
- ☆86Updated 2 years ago
- This project is trying to create a base vitis platform to run with DPU☆49Updated 5 years ago
- Aiming at an AI Chip based on RISC-V and NVDLA.☆21Updated 7 years ago
- Eyeriss chip simulator☆39Updated 5 years ago
- ☆42Updated 9 months ago
- ☆66Updated 3 years ago
- Provides the hardware code for the paper "EBPC: Extended Bit-Plane Compression for Deep Neural Network Inference and Training Accelerator…☆24Updated 5 years ago
- FireSim-NVDLA: NVIDIA Deep Learning Accelerator (NVDLA) Integrated with RISC-V Rocket Chip SoC Running on the Amazon FPGA Cloud☆165Updated 4 years ago
- Systolic-array based Deep Learning Accelerator generator☆28Updated 5 years ago
- ☆16Updated 6 years ago
- SAURIA (Systolic-Array tensor Unit for aRtificial Intelligence Acceleration) is an open-source Convolutional Neural Network accelerator b…☆79Updated 2 months ago
- ☆65Updated 5 years ago
- vector multiplication adder accelerator (using chisel 3 and RocketChip RoCC ) 向量乘法累加加速器☆53Updated 5 years ago
- Template for projects using the Hwacha data-parallel accelerator☆34Updated 5 years ago
- A parametric RTL code generator of an efficient integer MxM Systolic Array implementation for Xilinx FPGAs.☆30Updated 4 months ago