Alternatives and similar repositories for ITRI-OpenDLA:

Users that are interested in ITRI-OpenDLA are comparing it to the libraries listed below

• zeasa / nvdla-compiler
  ☆42Updated 5 years ago
• isuckatdrifting / Zeus
  NVDLA small config implementation on Zynq ZCU104 (evaluation)
  ☆23Updated 6 years ago
• soDLA-publishment / somnia
  Learn NVDLA by SOMNIA
  ☆33Updated 5 years ago
• VVViy / VVViy.github.io
  This is Max's blog, something interesting in it.
  ☆13Updated 2 years ago
• WuDan0399 / Integrate-NVDLA-and-TVM
  ☆30Updated 2 years ago
• jgoeders / dac_sdc_2020_designs
  Designs for finalist teams of the DAC System Design Contest
  ☆36Updated 4 years ago
• natu4u / GSOC_TensorCore
  TensorCore Vector Processor for Deep Learning - Google Summer of Code Project
  ☆22Updated 3 years ago
• DPCEKY / systolic-array
  HLS implemented systolic array structure
  ☆41Updated 7 years ago
• JunningWu / AIChip
  Aiming at an AI Chip based on RISC-V and NVDLA.
  ☆20Updated 7 years ago
• Caiyujie007 / OpenVPU
  This is an open CNN accelerator for everyone to use
  ☆14Updated 5 years ago
• jiaaom / HPDLA
  Systolic-array based Deep Learning Accelerator generator
  ☆25Updated 4 years ago
• LCAI-TIHU / HW
  LCAI-TIHU HW is an AI inference processor which is comprised of RISC-V cpu, nvdla, NoC bus, PCIe module, DDR, SRAM, bootROM, DMA and peri…
  ☆36Updated 2 years ago
• romulus0914 / CNN_VGG19_verilog
  Convolution Neural Network of vgg19 model in verilog
  ☆46Updated 7 years ago
• ac-optimus / Convolution-using-systolic-arrays
  ☆63Updated 6 years ago
• ljgibbslf / basic_cache_core
  ☆26Updated 4 years ago
• WenqiJiang / VGG16_FPGA_Accelerator
  A VGG accelerator by System Verilog on DE1-SoC FPGA. Row Stationary (RS) dataflow is adopted, and computations are based on fixed point 1…
  ☆30Updated 5 years ago
• harvard-acc / ESP_Systolic_Array_Accelerator
  ☆3Updated 3 years ago
• Starrynightzyq / soNN
  A Reconfigurable Accelerator for Deep Convolutional Neural Networks Implemented by Chisel3.
  ☆29Updated 3 years ago
• openasic-org / xkDLA
  xkDLA：XinKai Deep Learning Accelerator (RTL)
  ☆28Updated last year
• hyoukjun / microswitch-noc
  ☆26Updated 5 years ago
• SameLight / ITRI-OpenDLA
  Express DLA implementation for FPGA, revised based on NVDLA.
  ☆9Updated 5 years ago
• sharc-lab / FPGA_ECE8893
  ☆33Updated this week
• yuehniu / CNN.frequencyFPGA
  CNN Accelerator in Frequency Domain
  ☆12Updated 5 years ago
• yuhsaun-t / NPU-Architecture
  CS533 Course Project (ongoing) - Exploring Parallel Architectures for Neural Processing Unit Implementations
  ☆19Updated 7 years ago
• nqHITSZ / Systolic-Array
  course design
  ☆22Updated 7 years ago
• ic-lab-duth / NoCpad
  HLS for Networks-on-Chip
  ☆33Updated 4 years ago
• rgb000000 / eyeriss-chisel3
  eyeriss-chisel3
  ☆40Updated 2 years ago
• suchandler96 / gem5-NVDLA
  ☆29Updated 6 months ago
• hlslibs / hls_tutorials
  Tutorials on HLS Design
  ☆51Updated 5 years ago
• prasshantg / personal
  ☆16Updated 5 years ago