Alternatives and similar repositories for ITRI-OpenDLA

Users that are interested in ITRI-OpenDLA are comparing it to the libraries listed below

• soDLA-publishment / somnia
  Learn NVDLA by SOMNIA
  ☆33Updated 5 years ago
• SameLight / ITRI-OpenDLA
  Express DLA implementation for FPGA, revised based on NVDLA.
  ☆9Updated 5 years ago
• kinap / AES-Processor
  AES crypto engine written in System Verilog and emulated on the Mentor Veloce. First place winner of Mentor Graphics Need For Speed Emula…
  ☆16Updated 8 years ago
• WuDan0399 / Integrate-NVDLA-and-TVM
  ☆30Updated 2 years ago
• natu4u / GSOC_TensorCore
  TensorCore Vector Processor for Deep Learning - Google Summer of Code Project
  ☆21Updated 3 years ago
• VVViy / VVViy.github.io
  This is Max's blog, something interesting in it.
  ☆13Updated 2 years ago
• jiaaom / HPDLA
  Systolic-array based Deep Learning Accelerator generator
  ☆24Updated 4 years ago
• isuckatdrifting / Zeus
  NVDLA small config implementation on Zynq ZCU104 (evaluation)
  ☆23Updated 6 years ago
• ucb-bar / hwacha-template
  Template for projects using the Hwacha data-parallel accelerator
  ☆34Updated 4 years ago
• LCAI-TIHU / HW
  LCAI-TIHU HW is an AI inference processor which is comprised of RISC-V cpu, nvdla, NoC bus, PCIe module, DDR, SRAM, bootROM, DMA and peri…
  ☆37Updated 2 years ago
• Zaoldyeckk / High-Level-Synthesis-Flow-on-Zynq-using-Vivado-HLS
  This course provides professors with an understanding of high-level synthesis design methodologies necessary to develop digital systems u…
  ☆51Updated 6 years ago
• pulp-platform / rbe
  Reconfigurable Binary Engine
  ☆16Updated 4 years ago
• ic-lab-duth / NoCpad
  HLS for Networks-on-Chip
  ☆34Updated 4 years ago
• amohant4 / HLS_for_CNN
  This repo has codes for hardware accelerator design for CNNs using high level synthesis from Altera.
  ☆14Updated 7 years ago
• chenhaoc / cnnhwpe
  ☆65Updated 3 years ago
• zeasa / nvdla-compiler
  ☆44Updated 5 years ago
• hlslibs / hls_tutorials
  Tutorials on HLS Design
  ☆51Updated 5 years ago
• JunningWu / AIChip
  Aiming at an AI Chip based on RISC-V and NVDLA.
  ☆20Updated 7 years ago
• jgoeders / dac_sdc_2020_designs
  Designs for finalist teams of the DAC System Design Contest
  ☆37Updated 4 years ago
• openasic-org / xkDLA
  xkDLA：XinKai Deep Learning Accelerator (RTL)
  ☆31Updated last year
• pulp-platform / stream-ebpc
  Provides the hardware code for the paper "EBPC: Extended Bit-Plane Compression for Deep Neural Network Inference and Training Accelerator…
  ☆24Updated 4 years ago
• sazczmh / Ultra96-PYNQ_A-simple-summary
  Ultra96 PYNQ入门之一次简单的总结
  ☆14Updated 4 years ago
• plctlab / rvv-benchmark
  PLCT实验室 rvv-llvm 实现配套的 benchmark / testcases
  ☆22Updated 4 years ago
• gilani / fpfma
  Binary Single Precision Floating-point Fused Multiply-Add Unit Design (Verilog HDL)
  ☆19Updated 11 years ago
• Caiyujie007 / OpenVPU
  This is an open CNN accelerator for everyone to use
  ☆14Updated 5 years ago
• mnnuahg / StamicCGRA
  A static dataflow CGRA with dynamic dataflow execution capability
  ☆10Updated 3 years ago
• whatmough / CHIPKIT
  CHIPKIT: An agile, reusable open-source framework for rapid test chip development
  ☆41Updated 4 years ago
• LCAI-TIHU / SW
  LCAI-TIHU SW is a software stack of the AI inference processor based on RISC-V
  ☆23Updated 2 years ago
• gewuek / vitis_ai_custom_platform_flow
  This project is trying to create a base vitis platform to run with DPU
  ☆47Updated 4 years ago
• ultraembedded / core_axi_cache
  128KB AXI cache (32-bit in, 256-bit out)
  ☆49Updated 4 years ago