NVDLA small config implementation on Zynq ZCU104 (evaluation)
☆24Mar 25, 2019Updated 7 years ago
Alternatives and similar repositories for Zeus
Users that are interested in Zeus are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- A NVDLA Loadable Parser.☆13Mar 2, 2022Updated 4 years ago
- NVDLA is an Open source DL/ML accelerator, which is very suitable for individuals or college students. This is the NOTES when I learn and…☆232Dec 18, 2018Updated 7 years ago
- Express DLA implementation for FPGA, revised based on NVDLA.☆12Oct 17, 2019Updated 6 years ago
- HLS project modeling various sparse accelerators.☆12Jan 11, 2022Updated 4 years ago
- OpenDLA for trying the demo and FPGA solution☆17Jul 28, 2022Updated 3 years ago
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click. Zero configuration with optimized deployments.
- Zynq project to interface OV2640 camera module☆16Mar 11, 2016Updated 10 years ago
- FireSim-NVDLA: NVIDIA Deep Learning Accelerator (NVDLA) Integrated with RISC-V Rocket Chip SoC Running on the Amazon FPGA Cloud☆166Jan 16, 2022Updated 4 years ago
- zynqmp-zcu102 hacks☆20Sep 15, 2017Updated 8 years ago
- [TECS'23] A project on the co-design of Accelerators and CNNs.☆22Dec 10, 2022Updated 3 years ago
- Co-processor for whole genome alignment☆13Jun 6, 2020Updated 6 years ago
- A discussion group on Open Source Deep Learning Accelerator, with technical reports and potential hardware/software issues.☆146Nov 16, 2017Updated 8 years ago
- ☆17Nov 29, 2019Updated 6 years ago
- This is Max's blog, something interesting in it.☆13Jan 1, 2023Updated 3 years ago
- Port fpga-zynq (rocket-chip) to Xilinx ZYNQ Ultrascale+ board (ZCU102)☆65Mar 21, 2023Updated 3 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- ☆73Feb 16, 2023Updated 3 years ago
- run petalinux using docker tool☆29Feb 26, 2020Updated 6 years ago
- Sample scripts for FPGA-based AI Edge Contest 2019☆11Mar 20, 2020Updated 6 years ago
- Converting ss/vmess to clash proxies☆10May 19, 2022Updated 4 years ago
- transplant several overlays to s9_pynq board☆17Oct 31, 2020Updated 5 years ago
- ☆27Apr 28, 2020Updated 6 years ago
- OpenReroc (Open source Reconfigurable robot component)☆10Oct 17, 2016Updated 9 years ago
- A Reconfigurable Accelerator for Deep Convolutional Neural Networks Implemented by Chisel3.☆29Jul 14, 2021Updated 4 years ago
- Tutorial on installing QEMU to simulate Zynq Devices with Petalinux☆24Jun 6, 2017Updated 9 years ago
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- NVDLA (An Opensource DL Accelerator Framework) implementation on FPGA.☆388Dec 27, 2023Updated 2 years ago
- ChipScope / ILA using XVC (XIlinx Virtual Cable Over PCIe) with a PR (Partial Reconfiguration) design Example.☆15Jun 1, 2017Updated 9 years ago
- Ultra High Performance AXI4-based Direct Memory Access (DMA) Controller. This project was an interview assignment. Work in Progress.☆18Oct 19, 2024Updated last year
- The code for AIM2022 compressed image super-resolution☆11Nov 30, 2022Updated 3 years ago
- Optimized C++ ECDSA verifier for secp256k1☆12Mar 21, 2013Updated 13 years ago
- Benchmark framework of compute-in-memory based accelerators for deep neural network (inference engine focused)☆22Jun 1, 2021Updated 5 years ago
- Zynq Workshop for Beginners☆32May 21, 2015Updated 11 years ago
- This repository is an excuse to learn about Convolutional Neural Networks by implementing one in FPGA. The main goal is to learn, and to …☆12Jul 12, 2020Updated 5 years ago
- A Fix-pointed Rudimentary CNN Convolution Accelerator☆16Oct 7, 2020Updated 5 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- This is a circular buffer controller used in FPGA.☆35Jan 12, 2016Updated 10 years ago
- Face recognition with loss of softmax, sphereface, cosface, arcface in pytorch of python3☆10Apr 27, 2020Updated 6 years ago
- My implementation of an FPGA Deep Neural Network Hardware Accelerator, moved from my bitbucket☆29Jul 31, 2019Updated 6 years ago
- A configuration controller solution allowing a Zynq device to configure downstream FPGAs☆14Oct 5, 2015Updated 10 years ago
- Chinese Guide for Alveo Getting Started☆12May 18, 2020Updated 6 years ago
- Updated Xilinx PYNQ for Zynq + ZynqMP python HW acceleration development☆12Mar 16, 2018Updated 8 years ago
- This repository contains the hardware implementation for Static BFP convolution on FPGA☆10Oct 15, 2019Updated 6 years ago