isuckatdrifting / Zeus

Related projects ⓘ

Alternatives and complementary repositories for Zeus

• DPCEKY / systolic-array
  HLS implemented systolic array structure
  ☆41Updated 7 years ago
• zeasa / nvdla-compiler
  ☆42Updated 5 years ago
• jgoeders / dac_sdc_2020_designs
  Designs for finalist teams of the DAC System Design Contest
  ☆35Updated 4 years ago
• rgb000000 / eyeriss-chisel3
  eyeriss-chisel3
  ☆39Updated 2 years ago
• ic-lab-duth / NoCpad
  HLS for Networks-on-Chip
  ☆31Updated 3 years ago
• wzc810049078 / systolic-array-matrix-multiplier
  A systolic array matrix multiplier
  ☆23Updated 5 years ago
• kmanev / ZynqUSp-AXI-Speedtest
  ☆13Updated 4 years ago
• UCLA-VAST / FlexCNN
  ☆70Updated last year
• DNN-Accelerators / Open-Source-IPs
  ☆32Updated 5 years ago
• LCAI-TIHU / HW
  LCAI-TIHU HW is an AI inference processor which is comprised of RISC-V cpu, nvdla, NoC bus, PCIe module, DDR, SRAM, bootROM, DMA and peri…
  ☆31Updated last year
• linkuri267 / cnn_accelerator
  CNN accelerator using NoC architecture
  ☆15Updated 5 years ago
• GATECH-EIC / AutoDNNchip
  ☆69Updated 4 years ago
• chenhaoc / cnnhwpe
  ☆64Updated 2 years ago
• yuehniu / CNN.frequencyFPGA
  CNN Accelerator in Frequency Domain
  ☆10Updated 4 years ago
• pulp-platform / fpu
  ☆37Updated 5 years ago
• KastnerRG / Spector-HLS
  Contains FPGA benchmarks for Vivado HLS and Catapult HLS
  ☆24Updated 4 years ago
• pulp-platform / stream-ebpc
  Provides the hardware code for the paper "EBPC: Extended Bit-Plane Compression for Deep Neural Network Inference and Training Accelerator…
  ☆24Updated 4 years ago
• Parimala6 / Floating-point-MAC-verilog
  32 - bit floating point Multiplier Accumulator Unit (MAC)
  ☆24Updated 3 years ago
• harvard-acc / ESP_Systolic_Array_Accelerator
  ☆3Updated 3 years ago
• ac-optimus / Convolution-using-systolic-arrays
  ☆60Updated 5 years ago
• suchandler96 / gem5-NVDLA
  ☆22Updated last month
• harvard-acc / FlexASR
  FlexASR: A Reconfigurable Hardware Accelerator for Attention-based Seq-to-Seq Networks
  ☆42Updated 2 years ago
• THU-DSP-LAB / ventus-gpgpu-cpp-simulator
  Cycle-accurate C++ & SystemC simulator for the RISC-V GPGPU Ventus
  ☆19Updated 3 months ago
• govindjeevan / Weighted-Round-Robin-Arbiter
  Verilog Code and Logisim simulation of a Weighted Round Robit Arbiter circuit using digital components
  ☆18Updated 6 years ago
• diwu1990 / uSystolic-Sim
  A systolic array simulator for multi-cycle MACs and varying-byte words, with the paper accepted to HPCA 2022.
  ☆65Updated 3 years ago
• suoglu / Fixed-Floating-Point-Adder-Multiplier
  16-bit Adder Multiplier hardware on Digilent Basys 3
  ☆63Updated last year
• romulus0914 / CNN_VGG19_verilog
  Convolution Neural Network of vgg19 model in verilog
  ☆44Updated 6 years ago
• xliu0709 / WinoCNN
  An HLS based winograd systolic CNN accelerator
  ☆48Updated 3 years ago
• kkiningh / cs231n-project
  CNN accelerator
  ☆27Updated 7 years ago