isuckatdrifting / Zeus
NVDLA small config implementation on Zynq ZCU104 (evaluation)
☆23Updated 5 years ago
Alternatives and similar repositories for Zeus:
Users that are interested in Zeus are comparing it to the libraries listed below
- Designs for finalist teams of the DAC System Design Contest☆36Updated 4 years ago
- ☆14Updated 5 years ago
- ☆42Updated 5 years ago
- eyeriss-chisel3☆40Updated 2 years ago
- ☆70Updated 4 years ago
- HLS implemented systolic array structure☆41Updated 7 years ago
- HLS for Networks-on-Chip☆33Updated 4 years ago
- A VGG accelerator by System Verilog on DE1-SoC FPGA. Row Stationary (RS) dataflow is adopted, and computations are based on fixed point 1…☆30Updated 5 years ago
- ☆33Updated 6 years ago
- Contains FPGA benchmarks for Vivado HLS and Catapult HLS☆26Updated 4 years ago
- ☆71Updated 2 years ago
- An HLS based winograd systolic CNN accelerator☆50Updated 3 years ago
- Example of Tiny YOLO deployed using Xilinx BNN-PYNQ.☆30Updated 5 years ago
- ☆12Updated 9 months ago
- ☆26Updated 5 years ago
- ☆57Updated 4 years ago
- Provides the hardware code for the paper "EBPC: Extended Bit-Plane Compression for Deep Neural Network Inference and Training Accelerator…☆24Updated 4 years ago
- Convolution Neural Network of vgg19 model in verilog☆46Updated 7 years ago
- A systolic array matrix multiplier☆24Updated 5 years ago
- ☆41Updated 6 years ago
- [TECS'23] A project on the co-design of Accelerators and CNNs.☆20Updated 2 years ago
- ☆65Updated 2 years ago
- Light-weighted neural network inference for object detection on small-scale FPGA board☆91Updated 5 years ago
- ☆23Updated 3 years ago
- DMA controller for CNN accelerator☆13Updated 7 years ago
- FPGA and GPU acceleration of LeNet5☆35Updated 5 years ago
- CNN accelerator using NoC architecture☆16Updated 6 years ago
- ☆63Updated 6 years ago
- ☆81Updated last year
- tpu-systolic-array-weight-stationary☆22Updated 3 years ago