Alternatives and similar repositories for Zeus

Users that are interested in Zeus are comparing it to the libraries listed below

• DPCEKY / systolic-array
  HLS implemented systolic array structure
  ☆41Updated 7 years ago
• UCLA-VAST / FlexCNN
  ☆71Updated 2 years ago
• zeasa / nvdla-compiler
  ☆44Updated 5 years ago
• kmanev / ZynqUSp-AXI-Speedtest
  ☆14Updated 5 years ago
• ac-optimus / Convolution-using-systolic-arrays
  ☆65Updated 6 years ago
• rgb000000 / eyeriss-chisel3
  eyeriss-chisel3
  ☆41Updated 3 years ago
• bsc-loca / sauria
  SAURIA (Systolic-Array tensor Unit for aRtificial Intelligence Acceleration) is an open-source Convolutional Neural Network accelerator b…
  ☆51Updated 9 months ago
• wzc810049078 / systolic-array-matrix-multiplier
  A systolic array matrix multiplier
  ☆24Updated 5 years ago
• matutani / nocgen
  NoC (Network-on-Chip) generator that generates Verilog HDL model of NoC consisting of on-chip routers
  ☆65Updated 5 years ago
• ic-lab-duth / NoCpad
  HLS for Networks-on-Chip
  ☆35Updated 4 years ago
• hlslibs / hls_tutorials
  Tutorials on HLS Design
  ☆52Updated 5 years ago
• alexmr09 / Mixed-precision-Neural-Networks-on-RISC-V-Cores
  ☆30Updated last month
• harvard-acc / ESP_Systolic_Array_Accelerator
  ☆4Updated 4 years ago
• suoglu / Fixed-Floating-Point-Adder-Multiplier
  16-bit Adder Multiplier hardware on Digilent Basys 3
  ☆76Updated last year
• xliu0709 / WinoCNN
  An HLS based winograd systolic CNN accelerator
  ☆53Updated 3 years ago
• sharc-lab / FPGA_ECE8893
  ☆35Updated 3 months ago
• hyoukjun / microswitch-noc
  ☆27Updated 5 years ago
• chenhaoc / cnnhwpe
  ☆66Updated 3 years ago
• GATECH-EIC / AutoDNNchip
  ☆71Updated 5 years ago
• gem5-X / TiC-SAT
  ☆17Updated 2 months ago
• lllibano / SystolicArray
  A parametric RTL code generator of an efficient integer MxM Systolic Array implementation for Xilinx FPGAs.
  ☆23Updated 3 months ago
• DNN-Accelerators / Open-Source-IPs
  ☆33Updated 6 years ago
• jgoeders / dac_sdc_2020_designs
  Designs for finalist teams of the DAC System Design Contest
  ☆37Updated 5 years ago
• jha-lab / codebench
  [TECS'23] A project on the co-design of Accelerators and CNNs.
  ☆20Updated 2 years ago
• Starrynightzyq / soNN
  A Reconfigurable Accelerator for Deep Convolutional Neural Networks Implemented by Chisel3.
  ☆28Updated 4 years ago
• diwu1990 / uSystolic-Sim
  A systolic array simulator for multi-cycle MACs and varying-byte words, with the paper accepted to HPCA 2022.
  ☆79Updated 3 years ago
• sherylll / lenet5-accelerator
  FPGA and GPU acceleration of LeNet5
  ☆34Updated 6 years ago
• hyoukjun / DesignCNNAccelerators
  Lab code for three-day lecture, "Designing CNN Accelerators using Bluespec System Verilog", given at SNU in December 2017
  ☆30Updated 6 years ago
• harvard-acc / FlexASR
  FlexASR: A Reconfigurable Hardware Accelerator for Attention-based Seq-to-Seq Networks
  ☆46Updated 4 months ago
• Xilinx / ResNet50-PYNQ
  Quantized ResNet50 Dataflow Acceleration on Alveo, with PYNQ
  ☆58Updated 3 years ago