isuckatdrifting / ZeusLinks
NVDLA small config implementation on Zynq ZCU104 (evaluation)
☆23Updated 6 years ago
Alternatives and similar repositories for Zeus
Users that are interested in Zeus are comparing it to the libraries listed below
Sorting:
- HLS implemented systolic array structure☆41Updated 7 years ago
- ☆15Updated 5 years ago
- ☆46Updated 5 years ago
- ☆32Updated 3 months ago
- ☆34Updated 6 years ago
- Designs for finalist teams of the DAC System Design Contest☆37Updated 5 years ago
- ☆66Updated 6 years ago
- FlexASR: A Reconfigurable Hardware Accelerator for Attention-based Seq-to-Seq Networks☆48Updated 6 months ago
- ☆72Updated 2 years ago
- ☆66Updated 3 years ago
- SAURIA (Systolic-Array tensor Unit for aRtificial Intelligence Acceleration) is an open-source Convolutional Neural Network accelerator b…☆58Updated 11 months ago
- 16-bit Adder Multiplier hardware on Digilent Basys 3☆80Updated 2 years ago
- A systolic array matrix multiplier☆25Updated 6 years ago
- eyeriss-chisel3☆41Updated 3 years ago
- HLS for Networks-on-Chip☆36Updated 4 years ago
- ☆71Updated 5 years ago
- ☆17Updated 4 months ago
- NoC (Network-on-Chip) generator that generates Verilog HDL model of NoC consisting of on-chip routers☆67Updated 5 years ago
- An HLS based winograd systolic CNN accelerator☆54Updated 4 years ago
- Tutorials on HLS Design☆52Updated 5 years ago
- Light-weighted neural network inference for object detection on small-scale FPGA board☆93Updated 6 years ago
- A VGG accelerator by System Verilog on DE1-SoC FPGA. Row Stationary (RS) dataflow is adopted, and computations are based on fixed point 1…☆34Updated 5 years ago
- MAERI: A DNN accelerator with reconfigurable interconnects to support flexible dataflow (http://synergy.ece.gatech.edu/tools/maeri/)☆66Updated 3 years ago
- ☆27Updated 5 years ago
- A Reconfigurable Accelerator for Deep Convolutional Neural Networks Implemented by Chisel3.☆29Updated 4 years ago
- LCAI-TIHU HW is an AI inference processor which is comprised of RISC-V cpu, nvdla, NoC bus, PCIe module, DDR, SRAM, bootROM, DMA and peri…☆42Updated 2 years ago
- A parametric RTL code generator of an efficient integer MxM Systolic Array implementation for Xilinx FPGAs.☆26Updated 3 weeks ago
- Hardware accelerator for convolutional neural networks☆53Updated 3 years ago
- [TECS'23] A project on the co-design of Accelerators and CNNs.☆20Updated 2 years ago
- CNN Accelerator in Frequency Domain☆12Updated 5 years ago