DawnCarol / OpenC910_Modified
commit rtl and build cosim env
☆15Updated last year
Alternatives and similar repositories for OpenC910_Modified:
Users that are interested in OpenC910_Modified are comparing it to the libraries listed below
- ☆19Updated 2 years ago
- AXI master to AHB slave, support INCR/WRAP, out of standing, do not advanced feature such as support out of order, retry, split, etc☆39Updated 3 years ago
- DDR3 SDRAM Memory Controller Design & Synthesis using System Verilog☆31Updated 6 years ago
- ☆9Updated 4 years ago
- Verilog Code and Logisim simulation of a Weighted Round Robit Arbiter circuit using digital components☆18Updated 7 years ago
- ☆21Updated 5 years ago
- verification of simple axi-based cache☆18Updated 5 years ago
- ☆50Updated 2 years ago
- HYF's high quality verilog codes☆11Updated 4 months ago
- RTL code of some arbitration algorithm☆13Updated 5 years ago
- A VerilogHDL MCU Core based ARMv6 Cortex-M0☆21Updated 5 years ago
- AXI Interconnect☆47Updated 3 years ago
- ☆27Updated 4 years ago
- 异步FIFO的内部实现☆24Updated 6 years ago
- A generic implementation of AMBA AXI4 communication protocol. The design provides a master, a slave and an interconnect with multiple mas…☆38Updated 2 years ago
- ☆16Updated 6 years ago
- LCAI-TIHU HW is an AI inference processor which is comprised of RISC-V cpu, nvdla, NoC bus, PCIe module, DDR, SRAM, bootROM, DMA and peri…☆37Updated 2 years ago
- The memory model was leveraged from micron.☆22Updated 7 years ago
- this is an AHB to APB bridge with Synopsys VIP based test enviroment. RTL can be found from UVM website.☆16Updated 10 years ago
- SoC Based on ARM Cortex-M3☆30Updated 3 weeks ago
- Simple AMBA VIP, Include axi/ahb/apb☆20Updated 9 months ago
- 包括同步FIFO(输入输出位宽相同),异步FIFO(输入输出位宽相同),异步FIFO(能实现输出数据位宽是输入数据位宽的1/2或2倍)☆20Updated 2 years ago
- Generic AXI to AHB bridge☆16Updated 10 years ago
- 多核处理器 ;ring network , four core, shared space memory ,directory-based cache coherency☆23Updated 8 years ago
- ☆25Updated 3 years ago
- 本 工具用于自动生成一个Wallace Tree算法VerilogHDL代码实例,并附带了一些配套的工具和一个完整的VerilogHDL描述的乘法器。☆25Updated last year
- A Verification Platform for UDP Protocol Ethernet Module wrapped with AXI and APB bus based on UVM☆25Updated 2 years ago
- Base on Synopsys platform using VCS,DC,ICC,PT.☆11Updated 3 years ago
- ☆31Updated 5 years ago
- Build an open source, extremely simple DMA.☆21Updated 6 years ago