shalan / Chameleon_SoCLinks
AHB-Lite based SoC for IBEX/SWERV/VEXRISC/...
☆14Updated 7 months ago
Alternatives and similar repositories for Chameleon_SoC
Users that are interested in Chameleon_SoC are comparing it to the libraries listed below
Sorting:
- Extended and external tests for Verilator testing☆17Updated this week
- tools to help make the most of the limited space we have on the Google sponsored Efabless shuttles☆36Updated 2 years ago
- A 32 bit RISCV Based SOC with QSpi , Uart and 8 bit SDRAM Controller tagetted to efebless shuttle program☆21Updated 2 years ago
- Quick'n'dirty FuseSoC+cocotb example☆18Updated 11 months ago
- A Python package for generating HDL wrappers and top modules for HDL sources☆38Updated 2 weeks ago
- Pipelined FFT/IFFT 64 points processor☆11Updated 11 years ago
- Examples and design pattern for VHDL verification☆15Updated 9 years ago
- submission repository for efabless mpw6 shuttle☆30Updated last year
- SystemC to Verilog Synthesizable Subset Translator☆12Updated 2 years ago
- ☆10Updated 2 years ago
- ☆14Updated 7 months ago
- Python library for working Standard Delay Format (SDF) Timing Annotation files.☆30Updated last year
- SystemVerilog FSM generator☆32Updated last year
- SystemVerilog Linter based on pyslang☆31Updated 6 months ago
- WISHBONE Interconnect☆11Updated 8 years ago
- Common SystemVerilog RTL modules for RgGen☆13Updated 2 months ago
- UART cocotb module☆11Updated 4 years ago
- A padring generator for ASICs☆25Updated 2 years ago
- WISHBONE DMA/Bridge IP Core☆18Updated 11 years ago
- The open- MSP430 is an open-source 16-bit microcontroller core written in Verilog, that is compatible with the Texas Instruments MSP430 m…☆16Updated 3 years ago
- https://caravel-mgmt-soc-litex.readthedocs.io/en/latest/☆28Updated 9 months ago
- Common SystemVerilog package used by all RoaLogic IP with AMBA AHB3-Lite interfaces☆18Updated last year
- An open source, parameterized SystemVerilog digital hardware IP library☆30Updated last year
- Wishbone SATA Controller☆21Updated 3 weeks ago
- An SRAM IP Uniquely designed with open source tools. Static RAM is a type of random-access memory that uses latching circuitry (flip-flop…☆11Updated 5 years ago
- The first-ever opensource RTL core for PCIE EndPoint. Without vendor-locked HMs for Data Link, Transaction, Application layers; With stan…☆39Updated last week
- ☆17Updated last year
- Trying to verify Verilog/VHDL designs with formal methods and tools☆42Updated last year
- High speed C/C++ based behavioural VHDL/Verilog co-simulation memory model☆25Updated 4 months ago
- Generic AXI master stub☆19Updated 11 years ago