shalan / Chameleon_SoCLinks
AHB-Lite based SoC for IBEX/SWERV/VEXRISC/...
☆14Updated 6 months ago
Alternatives and similar repositories for Chameleon_SoC
Users that are interested in Chameleon_SoC are comparing it to the libraries listed below
Sorting:
- Extended and external tests for Verilator testing☆16Updated 2 weeks ago
- A Python package for generating HDL wrappers and top modules for HDL sources☆36Updated this week
- A 32 bit RISCV Based SOC with QSpi , Uart and 8 bit SDRAM Controller tagetted to efebless shuttle program☆21Updated 2 years ago
- Quick'n'dirty FuseSoC+cocotb example☆18Updated 10 months ago
- Pipelined FFT/IFFT 64 points processor☆11Updated 11 years ago
- tools to help make the most of the limited space we have on the Google sponsored Efabless shuttles☆36Updated 2 years ago
- UART cocotb module☆11Updated 4 years ago
- ☆17Updated 11 months ago
- Examples and design pattern for VHDL verification☆15Updated 9 years ago
- SoCGen is a tool that automates SoC design by taking in a JSON description of the system and producing the final GDS-II. SoCGen supports …☆39Updated 4 years ago
- ☆10Updated last year
- A padring generator for ASICs☆25Updated 2 years ago
- SystemVerilog FSM generator☆32Updated last year
- An SRAM IP Uniquely designed with open source tools. Static RAM is a type of random-access memory that uses latching circuitry (flip-flop…☆11Updated 5 years ago
- LibreSilicon's Standard Cell Library Generator☆20Updated this week
- ☆19Updated 11 years ago
- submission repository for efabless mpw6 shuttle☆30Updated last year
- Source-Opened RISCV for Crypto☆18Updated 3 years ago
- SystemC to Verilog Synthesizable Subset Translator☆10Updated 2 years ago
- Python library for working Standard Delay Format (SDF) Timing Annotation files.☆30Updated last year
- https://caravel-mgmt-soc-litex.readthedocs.io/en/latest/☆28Updated 8 months ago
- Common SystemVerilog package used by all RoaLogic IP with AMBA AHB3-Lite interfaces☆17Updated last year
- Trying to verify Verilog/VHDL designs with formal methods and tools☆42Updated last year
- Universal Advanced JTAG Debug Interface☆17Updated last year
- ☆10Updated 3 years ago
- AXI4-Compatible Verilog Cores, along with some helper modules.☆16Updated 5 years ago
- An open source, parameterized SystemVerilog digital hardware IP library☆29Updated last year
- SystemVerilog Linter based on pyslang☆31Updated 5 months ago
- Yosys plugin for logic locking and supply-chain security☆22Updated 6 months ago
- cryptography ip-cores in vhdl / verilog☆41Updated 4 years ago