RISC-V vector extension ISA simulation
☆18Jun 11, 2019Updated 7 years ago
Alternatives and similar repositories for rvv-simulator
Users that are interested in rvv-simulator are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- ☆10Sep 1, 2020Updated 6 years ago
- This is an read-only mirror of the gem5 simulator. The upstream repository is stored in https://gem5.googlesource.com, code reviews shoul…☆19Aug 21, 2021Updated 5 years ago
- fpga PCIE测速，采用riffa架构☆12Mar 15, 2021Updated 5 years ago
- Implements kernels with RISC-V Vector☆22Mar 24, 2023Updated 3 years ago
- ☆15Oct 27, 2026Updated last week
- Managed Database hosting by DigitalOcean • AdPostgreSQL, MySQL, MongoDB, Kafka, Valkey, and OpenSearch available. Automatically scale up storage and focus on building your apps.
- ☆13May 8, 2022Updated 4 years ago
- Direct Access Memory for MPSoC☆13Updated this week
- Original test vector of RISC-V Vector Extension☆14Mar 23, 2021Updated 5 years ago
- DMA controller for CNN accelerator☆15May 22, 2017Updated 9 years ago
- ☆16Apr 21, 2019Updated 7 years ago
- RISC-V implementation of the C/C++ Atomic operations library☆22Feb 11, 2019Updated 7 years ago
- R2MDC FFT/IFFT processor adaptive to 64/128/256/512 point☆19Dec 23, 2025Updated 10 months ago
- SCARV: a side-channel hardened RISC-V platform☆28Jan 11, 2023Updated 3 years ago
- RiVEC Bencmark Suite☆134Nov 27, 2024Updated last year
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click. Zero configuration with optimized deployments.
- ☆21Nov 18, 2022Updated 3 years ago
- SSRV(Super-Scalar RISC-V) --- Super-scalar out-of-order RV32IMC CPU core, 6.4 CoreMark/MHz.☆239Aug 25, 2020Updated 6 years ago
- PLCT实验室 rvv-llvm 实现配套的 benchmark / testcases☆21Nov 26, 2020Updated 5 years ago
- RISC-V vector and other assembly code examples☆28Nov 4, 2020Updated 6 years ago
- GateMate's PHY Interface for PCI Express (PIPE)☆15Oct 21, 2026Updated 2 weeks ago
- SoCGen is a tool that automates SoC design by taking in a JSON description of the system and producing the final GDS-II. SoCGen supports …☆41Dec 4, 2020Updated 5 years ago
- Class project for COMP-781, Robotics. This is a CUDA-based collision detector for motion planning.☆13Apr 29, 2019Updated 7 years ago
- TEESec: Pre-Silicon Vulnerability Discovery for Trusted Execution Environments☆12Apr 4, 2024Updated 2 years ago
- ☆13Jun 9, 2022Updated 4 years ago
- Virtual machines for every use case on DigitalOcean • AdGet dependable uptime with 99.99% SLA, simple security tools, and predictable monthly pricing with DigitalOcean's virtual machines, called Droplets.
- Full Support 32bit RISC-V in LLVM and CLANG for Vector Extension☆43Dec 21, 2020Updated 5 years ago
- Implements Mutex, Semaphore and exclusive ReadModifyWrite operations on ARM Cortex-M3 and Cortex-M4☆11Feb 28, 2019Updated 7 years ago
- Code for experiments referenced in the Usenix Security 2017 paper "Strong and Efficient Cache Side-Channel Protection using Hardware Tran…☆15Sep 8, 2022Updated 4 years ago
- RISC-V SIMD Superscalar Dual-Issue Processor☆31Apr 24, 2025Updated last year
- A lightweight core for the CV32E40 implementing the RISC-V vector extension specification. (v0.8)☆35Jan 19, 2021Updated 5 years ago
- Nuclei AI Library Optimized For RISC-V Vector☆16Oct 15, 2025Updated last year
- An instruction set simulator based on DBT-RISE implementing the RISC-V ISA☆37Oct 26, 2026Updated last week
- A C++ PMU and/or PDC Stream Simulator for IEEE C37.118.2☆13May 21, 2019Updated 7 years ago
- ☆15Oct 2, 2023Updated 3 years ago
- GPUs on demand by Runpod - Special Offer Available • AdRun AI, ML, and HPC workloads on powerful cloud GPUs—without limits or wasted spend. Deploy GPUs in under a minute and pay by the second.
- libopencm3 c++ wrappers☆10Dec 25, 2020Updated 5 years ago
- RCP over DDS C++ API☆13Jan 27, 2016Updated 10 years ago
- ☆11Jan 9, 2021Updated 5 years ago
- A template for developing custom FIRRTL transforms☆10Jan 30, 2020Updated 6 years ago
- Functional Verification of Physical Layer of PCI Express Gen5.0 Graduation Project Using UVM☆37Jul 17, 2025Updated last year
- Vector processor for RISC-V vector ISA☆147Oct 19, 2020Updated 6 years ago
- A Symbolic Emulator for Shuffle Synthesis on the NVIDIA PTX Code☆16Mar 19, 2023Updated 3 years ago