raymondrc / riscv-isa-extension-for-SM4Links
RISC-V instruction set extensions for SM4 block cipher
☆20Updated 5 years ago
Alternatives and similar repositories for riscv-isa-extension-for-SM4
Users that are interested in riscv-isa-extension-for-SM4 are comparing it to the libraries listed below
Sorting:
- Verilog implementation of 1024 bit Hybrid Montgomery Multiplication/Exponentiation☆11Updated 5 years ago
- verification of simple axi-based cache☆18Updated 6 years ago
- Implementation of cryptographic algorithm with verilog hdl(such as des,aes,sha,rsa,ecc etc.)☆41Updated 5 years ago
- 128KB AXI cache (32-bit in, 256-bit out)☆53Updated 4 years ago
- ☆16Updated 6 years ago
- FPGA implementation of Chinese SM4 encryption algorithm.☆56Updated 7 years ago
- Linux-capable superscalar out-of-order RISC core (with Cache& MMU) and SoC, having been verified on Xilinx Kintex-7 FPGA.☆55Updated last year
- RISC-V IOMMU in verilog☆20Updated 3 years ago
- The official NaplesPU hardware code repository☆19Updated 6 years ago
- A simple, scalable, source-synchronous, all-digital DDR link☆30Updated 4 months ago
- Verilog Code for a JPEG Decoder☆34Updated 7 years ago
- ☆10Updated 3 years ago
- ☆14Updated 6 years ago
- Description of Chinese SM3 Hash algorithm with Verilog HDL☆51Updated 7 years ago
- ☆17Updated 10 years ago
- JPEG Compression RTL implementation☆11Updated 8 years ago
- IOPMP IP☆21Updated 4 months ago
- LCAI-TIHU HW is an AI inference processor which is comprised of RISC-V cpu, nvdla, NoC bus, PCIe module, DDR, SRAM, bootROM, DMA and peri…☆42Updated 2 years ago
- Network on Chip for MPSoC☆28Updated last week
- Verilog Implementation of modular exponentiation using Montgomery multiplication☆36Updated 11 years ago
- System Verilog and Emulation. Written all the five channels.☆35Updated 8 years ago
- Open-Channel Open-Way Flash Controller☆19Updated 4 years ago
- DDR3 SDRAM Memory Controller Design & Synthesis using System Verilog☆31Updated 7 years ago
- ☆13Updated 10 years ago
- 异步FIFO的内部实现☆25Updated 7 years ago
- ☆30Updated 3 weeks ago
- AXI X-Bar☆19Updated 5 years ago
- ☆31Updated 5 years ago
- Verilog HDL implementation of Elliptic Curve Cryptography (ECC) over GF(2^163)☆22Updated 8 years ago
- DDR4 Simulation Project in System Verilog☆42Updated 11 years ago