RISC-V instruction set extensions for SM4 block cipher
☆21Mar 6, 2020Updated 6 years ago
Alternatives and similar repositories for riscv-isa-extension-for-SM4
Users that are interested in riscv-isa-extension-for-SM4 are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Verilog Implementation of SM4 s-box☆22Jun 24, 2019Updated 7 years ago
- FPGA implementation of Chinese SM4 encryption algorithm.☆57Mar 11, 2018Updated 8 years ago
- Description of Chinese SM3 Hash algorithm with Verilog HDL☆55Aug 5, 2018Updated 8 years ago
- CORDIC VLSI-IP for deep learning activation functions☆15Jul 13, 2019Updated 7 years ago
- ☆12Apr 29, 2022Updated 4 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- Formal Verification of RISC V IM Processor☆11Mar 27, 2022Updated 4 years ago
- Verilog Modules for DSP functions and other common tasks to make FPGA development easier and more fun.☆20Jun 7, 2015Updated 11 years ago
- An OCaml extension for RISC-V☆16Nov 6, 2020Updated 5 years ago
- CNN accelerator using NoC architecture☆18Dec 6, 2018Updated 7 years ago
- wolfSSL SM cipher implementations☆22Updated this week
- M-extension for RISC-V cores.☆32Nov 21, 2024Updated last year
- AHB-Lite based SoC for IBEX/SWERV/VEXRISC/...☆13Mar 28, 2025Updated last year
- An FPGA-based RISC-V CPU☆16Dec 7, 2021Updated 4 years ago
- [HISTORICAL] A Lightweight (RISC-V) ISA Extension for AES and SM4☆39Feb 4, 2021Updated 5 years ago
- End-to-end encrypted cloud storage - Proton Drive • AdSpecial offer: 40% Off Yearly / 80% Off First Month. Protect your most important files, photos, and documents from prying eyes.
- VGA LCD Core (OpenCores)☆15May 22, 2018Updated 8 years ago
- Computer architecture learning environment using FPGAs☆15May 17, 2021Updated 5 years ago
- JPEG Compression RTL implementation☆11Aug 19, 2017Updated 8 years ago
- A simple, scalable, source-synchronous, all-digital DDR link☆40Updated this week
- A trivial riscv cpu with tomasulo algorithm implemented in Verilog HDL. Support out-of-order execution and pipline and can run in FPGA wi…☆16Jan 4, 2020Updated 6 years ago
- RISC-V模拟器，相关硬件实现`riscv-isa-sim`以及模拟器pk, bbl的指导手册☆54Apr 11, 2020Updated 6 years ago
- [HISTORICAL] FIPS and higher-level algorithm tests for RISC-V Crypto Extension☆29Jul 23, 2024Updated 2 years ago
- ☆11Jul 25, 2018Updated 8 years ago
- zqh_riscv is an open source SOC system based on riscv core and tilelink NOC bus. coding with PHGL language(python DSL language). this pro…☆40Sep 21, 2021Updated 4 years ago
- Serverless GPU API endpoints on Runpod - Get Bonus Credits • AdSkip the infrastructure headaches. Auto-scaling, pay-as-you-go, no-ops approach lets you focus on innovating your application.
- This project implemented an unoptimized simple convolutional neural network in ZYNQ's PL and realized data transmission through axidma dr…☆12Aug 5, 2018Updated 8 years ago
- git clone of http://code.google.com/p/axi-bfm/☆18May 21, 2013Updated 13 years ago
- Partial Verilog implimentation of a WiMAX OFDM Phy☆19May 28, 2012Updated 14 years ago
- Implementation of cryptographic algorithm with verilog hdl(such as des,aes,sha,rsa,ecc etc.)☆43Dec 1, 2019Updated 6 years ago
- 32-bit soft RISCV processor for FPGA applications☆19Nov 25, 2023Updated 2 years ago
- SiFive HiFive1 Rev B ESP32 - WiFi connection demo☆19Dec 8, 2019Updated 6 years ago
- ☆16Apr 21, 2019Updated 7 years ago
- Open Source Chip Project by University (OSCPU) - Zhoushan Core☆54Jul 23, 2022Updated 4 years ago
- ☆18Apr 5, 2015Updated 11 years ago
- Proton VPN Special Offer - Get 70% off • AdSpecial partner offer. Trusted by over 100 million users worldwide. Tested, Approved and Recommended by Experts.
- RISC-V IOMMU in verilog☆22Jun 18, 2022Updated 4 years ago
- 全方位控诉Windows的使用和开发体验☆12Jun 30, 2020Updated 6 years ago
- ☆17Apr 7, 2022Updated 4 years ago
- Antelope cryptography library for ECC, RSA and SHA-3☆10Mar 12, 2025Updated last year
- masked, bit-sliced AES-128 demo code☆15Jan 10, 2025Updated last year
- RTL Verilog library for various DSP modules☆99Feb 17, 2022Updated 4 years ago
- Implementation network trimming using pytorch☆15Apr 20, 2020Updated 6 years ago