RISC-V instruction set extensions for SM4 block cipher
☆22Mar 6, 2020Updated 6 years ago
Alternatives and similar repositories for riscv-isa-extension-for-SM4
Users that are interested in riscv-isa-extension-for-SM4 are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Verilog Implementation of SM4 s-box☆22Jun 24, 2019Updated 7 years ago
- FPGA implementation of Chinese SM4 encryption algorithm.☆57Mar 11, 2018Updated 8 years ago
- Description of Chinese SM3 Hash algorithm with Verilog HDL☆56Aug 5, 2018Updated 8 years ago
- CORDIC VLSI-IP for deep learning activation functions☆15Jul 13, 2019Updated 7 years ago
- FIR,FFT based on Verilog☆14Dec 3, 2017Updated 8 years ago
- Deploy open-source AI quickly and easily - Special Bonus Offer • AdRunpod Hub is built for open source. One-click deployment and autoscaling endpoints without provisioning your own infrastructure.
- Verilog Modules for DSP functions and other common tasks to make FPGA development easier and more fun.☆20Jun 7, 2015Updated 11 years ago
- An OCaml extension for RISC-V☆16Nov 6, 2020Updated 6 years ago
- DMA controller for CNN accelerator☆15May 22, 2017Updated 9 years ago
- RiscV cpu on FPGA☆13Apr 23, 2022Updated 4 years ago
- CNN accelerator using NoC architecture☆18Dec 6, 2018Updated 7 years ago
- AHB-Lite based SoC for IBEX/SWERV/VEXRISC/...☆13Mar 28, 2025Updated last year
- M-extension for RISC-V cores.☆33Nov 21, 2024Updated last year
- 机器人使用了Xilinx的SPARTAN-6系列芯片以及ISE设计工具对机器人控制电路进行了设计和仿真,验证了电路的正确性和可靠性。同时机器人使用了温湿度传感器、人体感应传感器、超声波传感器、震动传感器、有毒气体传感器等,可以对灾区的环境和受困人员进行多方面的检测和响应。还…☆12Nov 15, 2023Updated 2 years ago
- VGA LCD Core (OpenCores)☆15May 22, 2018Updated 8 years ago
- Serverless GPU API endpoints on Runpod - Get Bonus Credits • AdSkip the infrastructure headaches. Auto-scaling, pay-as-you-go, no-ops approach lets you focus on innovating your application.
- An FPGA-based RISC-V CPU☆16Dec 7, 2021Updated 4 years ago
- [HISTORICAL] A Lightweight (RISC-V) ISA Extension for AES and SM4☆40Feb 4, 2021Updated 5 years ago
- JPEG Compression RTL implementation☆11Aug 19, 2017Updated 9 years ago
- RISC-V模拟器,相关硬件实现`riscv-isa-sim`以及模拟器pk, bbl的指导手册☆53Apr 11, 2020Updated 6 years ago
- Accelerating the AES algorithm on an FPGA and comparing the speedup with both AES and Modified AES algorithms☆36Dec 10, 2021Updated 4 years ago
- ☆12Oct 8, 2021Updated 5 years ago
- yolov5-acceleration-fpga☆11Jun 25, 2025Updated last year
- A Direct Memory Access Controller (DMAC) with AHB-lite bus interface☆19Oct 6, 2024Updated 2 years ago
- Studies on basic hardware and software edge detection algorithms for future Stochastic Computing applications☆10Jul 11, 2021Updated 5 years ago
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- A trivial riscv cpu with tomasulo algorithm implemented in Verilog HDL. Support out-of-order execution and pipline and can run in FPGA wi…☆17Jan 4, 2020Updated 6 years ago
- The goal of this design is to use the PYNQ-Z2 development board to design a general convolution neural network accelerator. And through r…☆12Sep 30, 2020Updated 6 years ago
- [HISTORICAL] FIPS and higher-level algorithm tests for RISC-V Crypto Extension☆29Jul 23, 2024Updated 2 years ago
- LeNet-5 use c achieve☆13Jan 10, 2020Updated 6 years ago
- Partial Verilog implimentation of a WiMAX OFDM Phy☆19May 28, 2012Updated 14 years ago
- A CORDIC implementation of square root Verilog calculation on Quartus Prime 16.0, with ability to simulate on ModelSim as well.☆19Jul 24, 2021Updated 5 years ago
- Implementation of cryptographic algorithm with verilog hdl(such as des,aes,sha,rsa,ecc etc.)☆43Dec 1, 2019Updated 6 years ago
- zqh_riscv is an open source SOC system based on riscv core and tilelink NOC bus. coding with PHGL language(python DSL language). this pro…☆42Sep 21, 2021Updated 5 years ago
- A Fix-pointed Rudimentary CNN Convolution Accelerator☆16Oct 7, 2020Updated 6 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- SM4加密解密算法Verilog代码实现☆13Jun 5, 2024Updated 2 years ago
- Stochasm plugin for VCVRack providing modules based around stochastic computing.☆19Oct 8, 2019Updated 7 years ago
- Synthesis tool for stochastic computing☆22Sep 4, 2019Updated 7 years ago
- CNN-Accelerator based on FPGA developed by verilog HDL.☆48Apr 10, 2020Updated 6 years ago
- Yet another filesystem-based adventure game inspired by magic tower.☆12Jun 12, 2018Updated 8 years ago
- 32-bit soft RISCV processor for FPGA applications☆20Nov 25, 2023Updated 2 years ago
- ☆27Oct 21, 2022Updated 4 years ago